| Patent application number | Description | Published |
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| 20080201683 | Method of Generating Wiring Routes with Matching Delay in the Presence of Process Variation - A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse. | 08-21-2008 |
| 20080216036 | SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS - A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter. | 09-04-2008 |
| 20080250279 | Method of Increasing Path Coverage in Transition Test Generation - A method for automatically generating test patterns for digital logic circuitry using an automatic test pattern generation tool. The method includes generating test patterns and applying faulty behavior to various paths within the digital logic circuitry. As each circuit path is tested, tested circuit nodes along the circuit path are marked as “exercised.” Subsequent test paths are assembled by avoiding marked circuit nodes. In this manner, coverage of paths tested may be increased and many circuit nodes can be tested efficiently. | 10-09-2008 |
| 20080250370 | REPRESENTING AND PROPAGATING A VARIATIONAL VOLTAGE WAVEFORM IN STATISTICAL STATIC TIMING ANALYSIS OF DIGITAL CIRCUITS - An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is configured to generate a variational waveform model that approximate arbitrary waveform transformations of waveforms at nodes of a digital circuit. The variational waveform model transforms a nominal waveform into a perturbed waveform in accordance with a plurality of waveform transformation operators that account for variations that occur between the nominal waveform and the perturbed waveform. A variational waveform propagating component is configured to propagate variational waveforms through a timing arc from at least one input to at least one output of the digital circuit in accordance with the variational waveform model. | 10-09-2008 |
| 20080263488 | METHOD FOR GENERATING A SKEW SCHEDULE FOR A CLOCK DISTRIBUTION NETWORK CONTAINING GATING ELEMENTS - A method for generating a skew schedule for a clock distribution network generates a schedule that accounts for both the timing requirements of the memory elements at the endpoints of the clock distribution network and the timing requirements of the gating signals that feed clock gates and other clock control elements within the clock distribution network. The method provides a total solution to the skew scheduling problem by way of a two-phase iterative process. The two phases of the process alternately keep track of the schedule generated by first taking the gating elements of the clock distribution network into account, followed by balancing any remaining skew that may exist on the memory elements of the same clock distribution network. Finally, the method describes a procedure to post-process the skew schedule to ensure that it can be implemented using a clock tree generation tool. | 10-23-2008 |
| 20080270962 | STATIC TIMING SLACKS ANALYSIS AND MODIFICATION - A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path. | 10-30-2008 |
| 20080313590 | METHOD AND SYSTEM FOR EVALUATING TIMING IN AN INTEGRATED CIRCUIT - Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path. | 12-18-2008 |
| 20090132982 | METHOD FOR OPTIMIZING AN UNROUTED DESIGN TO REDUCE THE PROBABILITY OF TIMING PROBLEMS DUE TO COUPLING AND LONG WIRE ROUTES - A method and a system is described to predict effects of coupling on timing by estimating the delta delay and delta slack that can occur due to coupling on any net, for optimization to minimize the sensitivity of slack to potential coupling violations. The invention protects against other unexpected increases in effective load capacitance, such as those due to unexpectedly long wire routes. It also estimates the delay impact of a single ‘fault’ or ‘event’, such as a coupling event or unexpectedly long wires routes, including the impact of slew propagation. | 05-21-2009 |
| 20090276743 | SYSTEM AND METHOD FOR COMPUTING PROXY SLACK DURING STATISTIC ANALYSIS OF DIGITAL INTEGRATED CIRCUITS - A method of optimizing timing of signals within an integrated circuit design using proxy slack values propagates signals through the integrated circuit design to output timing signals. For early mode timing analysis, the method sets an early proxy slack value to zero if the late slack value is less than zero. Otherwise, if the late slack value is not less than zero, the method restricts the early proxy slack value to a maximum of the early slack value and the negative of the late slack value. To the contrary, for late mode timing analysis, the method sets a late proxy slack value to zero if the early slack value is less than zero. Otherwise, if the early proxy slack value is not less than zero, the method restricts the late proxy slack value to a maximum of the late slack value and the negative of the early slack value. | 11-05-2009 |
| 20090278222 | INTEGRATED CIRCUIT WITH UNIFORM POLYSILICON PERIMETER DENSITY, METHOD AND DESIGN STRUCTURE - Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve the desired decoupling capacitance. Then, local polysilicon perimeter densities of the blocks are determined and, as necessary, the decoupling capacitor blocks are reconfigured in order to adjust for differences in the local polysilicon perimeter densities. This reconfiguring is performed in a manner that essentially maintains the desired decoupling capacitance. Due to the across-chip polysilicon perimeter density uniformity, functional devices in different regions of the chip will exhibit limited performance parameter variations (e.g., limited threshold voltage variations). Also disclosed herein are embodiments of an integrated circuit structure formed according to the method embodiments and a design structure for the integrated circuit. | 11-12-2009 |
| 20090282380 | METHOD OF LAYING OUT INTEGRATED CIRCUIT DESIGN BASED ON KNOWN POLYSILICON PERIMETER DENSITIES OF INDIVIDUAL CELLS - Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cells to drive placement of those cells on a chip (i.e., to drive floor-planning). The method embodiments can be used to achieve approximately uniform across-chip polysilicon perimeter density and, thereby to limit performance parameter variations between functional devices that are attributable to variations in polysilicon perimeter density. Alternatively, the method embodiments can be used to selectively control variations in the average polysilicon perimeter density of different regions of a chip and, thereby to selectively control certain performance parameter variations between functional devices located in those different regions. | 11-12-2009 |
| 20090307645 | METHOD AND SYSTEM FOR ANALYZING CROSS-TALK COUPLING NOISE EVENTS IN BLOCK-BASED STATISTICAL STATIC TIMING - A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis. | 12-10-2009 |
| 20100180242 | Method and system for efficient validation of clock skews during hierarchical static timing analysis - A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis. | 07-15-2010 |
| 20100180244 | Method For Efficiently Checkpointing And Restarting Static Timing Analysis Of An Integrated Circuit Chip - A method for loading checkpoint timing in an environment where the boundary arrival times, slews, required arrival times, or loads differ from the checkpoint run. A timing checkpoint file generated for one or more hierarchical modules, during which each input is assigned a unique phase tag. The association of unique phase tags allows subsequent restart analyses to efficiently adjust the checkpoint timing in relation to the restart timing environment. In the restart run, one or more such checkpoint files is read, during which an initial propagation of arrival, required arrivals and slew times are performed, followed by a local re-update based on adjusted arrival times and the required arrival times. Finally, if multiple hierarchical modules are updated, a global recalculation of timing values is performed based on a slack change threshold in order to determine whether any new timing failures have been introduced. | 07-15-2010 |
| 20110077882 | SYSTEM AND METHOD FOR ESTIMATING LEAKAGE CURRENT OF AN ELECTRONIC CIRCUIT - Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit. Then, for each state of each driven net-bounded partition, the leakage current of the driven net-bounded partition and the state probability are multiplied together. The results are then aggregated. | 03-31-2011 |
