| Patent application number | Description | Published |
|---|
| 20090051429 | HIGH RESOLUTION VARIABLE GAIN CONTROL - A gain circuit includes an analog section with variable gain and a digital section with variable gain. The gain steps for the digital section have a higher resolution than the gain steps for the analog section. In some implementations, gain steps can be achieved much finer than 0.1 db or less without sensitivity to device tolerances. | 02-26-2009 |
| 20090058531 | VARIABLE GAIN AMPLIFIER - Techniques and systems for receiving a signal at a first component with an adjustable gain, and adjusting the gain of the first component to a first gain value using a first gain step. Amplifying the signal with the first gain value, generating a first amplified signal, and receiving the first amplified signal at a second component with an adjustable gain. Adjusting a gain of the second component to a second gain value using a second gain step. The net gain step is smaller than one of the first or second gain step. Amplifying the first amplified signal with the second gain value to generate a second amplified signal, and receiving the second amplified signal at a filtering component. A transient response introduced by the filtering component on the second amplified signal is smaller than the transient response that would be introduced by the filtering component on the first amplified signal. | 03-05-2009 |
| 20090085545 | VOLTAGE REGULATOR - In some implementations, a system includes a low-power voltage regulator that can switch between three power modes: a power shutdown mode, a low power mode, and a higher power mode. The system includes a selector coupled to the voltage regulator to switch between the low power mode and the higher power mode, and a switch to switch between the power shutdown mode and the low or higher power mode. The system also has a control circuit to control the switch and the selector to control operation of the voltage regulator in any of the three power modes. A total current used in the voltage regulator in the low power mode is on the order of microamps or nanoamps. The voltage regulator in the low power mode has two to more orders of magnitude of lower current use than the voltage regulator in the higher power mode. | 04-02-2009 |
| 20090085622 | PHASE-LOCKED LOOP START-UP TECHNIQUES - Implementations feature systems and techniques for phase-locked loops (PLLs). In some aspects, implementations feature a system that has a PLL circuit including an oscillator and programmable reference frequency divider circuit or a programmable feedback frequency divider circuit. The PLL includes a control circuit to reduce a time required for a PLL settling time by programming a division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit to target the oscillator to operate outside of a system operating frequency range of the oscillator during start-up of PLL operations. The control circuit can program another division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit after stabilization of the variable oscillator. | 04-02-2009 |
| 20090085671 | LOAD INDUCTOR SHARING - Sharing one or more load inductors comprises receiving a first input signal at a first terminal of a first amplifier and amplifying the first input signal using the first amplifier. The first amplifier is coupled to one or more load inductors at a second terminal of the first amplifier and is coupled to one or more dedicated source inductors at a third terminal of the first amplifier. Also, a second input signal is received at a first terminal of a second amplifier amplifying the second input signal using the second amplifier. The second amplifier is coupled to the one or more load inductors at a second terminal of the second amplifier and is coupled to one or more dedicated source inductors at a third terminal of the second amplifier. | 04-02-2009 |
| 20090085789 | Analog To Digital Converter - An ADC, such as a CT SD-ADC, includes a clock generation circuit that produces charging and discharging clock signals such that a settling time for an integrator in the ADC is increased. The clock signals may control a feedback SD-DAC in the CT SD-ADC. The clock signals also may be asymmetric and/or may result in the settling time of the integrator being greater than half the system clock. | 04-02-2009 |
| 20090088091 | Transmitter for Multiple Standards - Generally, implementations provide a circuit framework that uses phase and amplitude modulation with several voltage-controlled-oscillators (VCOs) and corresponding variable gain amplifiers (VGAs) to generate and amplitude and phase modulated signals that are summed to an output signal for a transmitter circuit. The implementations can involve decomposing an input signal into a number of decomposed signals using a signal decomposer component, in which each of decomposed signals includes phase and amplitude information. The signal decomposer component can interact with each of the VCOs and corresponding VGAs to conduct the phase and amplitude modulation for the amplitude and phase modulated signals. The multiple standard transmitter circuit can be used for one or more communication standards, such as Global System for Mobile Communications (GSM), a Wideband Code Division Multiple Access (WCDMA), or High-Speed Uplink Packet Access (HSUPA), among others. | 04-02-2009 |
| 20090088110 | RADIO FREQUENCY RECEIVER ARCHITECTURE - A radio frequency receiver includes a passive mixer configured to receive and RF signal and a low input impedance circuit configured to receive the output of the passive mixer. | 04-02-2009 |
| 20090088121 | High Linearity and Low Noise Mixer - Circuits and methods for a mixer circuit involve having a first transistor with first and second terminals, where the first terminal is configured to handle an input RF signal. The mixer has a second transistor including a first terminal coupled to the second terminal of the first transistor, a second terminal configured to handle an input oscillator signal, and a third terminal configured to output an intermediate frequency (IF) signal. The IF signal includes a mixed product of the input RF signal and the input oscillator signal. A gate oxide thickness of the first transistor is less than a gate oxide thickness of the second transistor to provide enhanced linearity and a low noise figure. One or more of the mixers can be implemented in a receiver design. | 04-02-2009 |
