| Patent application number | Description | Published |
|---|
| 20080243453 | CAPACITANCE MODELING - A method of modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-chip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves as a perfect dielectric. It is assumed that the surrounding dielectric material is a first dielectric with a first permittivity (ε | 10-02-2008 |
| 20080244485 | CAPACITANCE MODELING - A method of modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-clip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves as a perfect dielectric. It is assumed that the surrounding dielectric material is a first dielectric with a first permittivity (∈ | 10-02-2008 |
| 20080297261 | Circuits and Methods for Implementing Transformer-Coupled Amplifiers at Millimeter Wave Frequencies - Circuits and methods are provided for building integrated transformer-coupled amplifiers with on-chip transformers that are designed to resonate or otherwise tune parasitic capacitances to achieve frequency tuning of amplifiers at millimeter wave operating frequencies. | 12-04-2008 |
| 20090150848 | Topologies and Methodologies for AMS Integrated Circuit Design - A tool for analog and mixed signal circuits includes a unit enabling a user to identify one or more critical interconnect lines in a chip architecture and one or more selectable, predefined topologies for said critical interconnect lines. Each topology includes one or more signal wires and a current return path. A majority of the electric field lines are contained within the boundary of the topology. The invention also includes a method for designing analog and mixed signal (AMS) integrated circuits (IC), including defining a chip architecture and a floor plan, identifying one or more critical interconnect lines and selecting pre-designed transmission line topologies for the critical interconnect lines. | 06-11-2009 |
| 20090158227 | METHOD AND SYSTEM FOR CALCULATING HIGH FREQUENCY LIMIT CAPACITANCE AND INDUCTANCE FOR COPLANAR ON-CHIP STRUCTURE - Capacitance and inductance expressions used for modeling critical on-chip metal interconnects. A method for calculating high frequency limit capacitances C | 06-18-2009 |
| 20100013459 | CIRCUITS AND METHODS FOR HIGH-EFFICIENCY ON-CHIP POWER DETECTION - Power detector integrally formed within a printed transmission line to capacitively couple a portion of signal power propagating on the printed transmission line and a power detector circuit that receives coupled power output from the power detector to detect a power level of the signal power. The power detector is designed such that capacitance of the coupling capacitor is absorbed into a distributed capacitance of the transmission line to maintain continuity of a characteristic impedance of the transmission line. | 01-21-2010 |
| 20110072408 | METHOD AND SYSTEM FOR DESIGN AND MODELING OF TRANSMISSION LINES - A method and system for design and modeling of transmission lines are provided. The method includes providing a set of models of core structures ( | 03-24-2011 |
| 20110179392 | LAYOUT DETERMINING FOR WIDE WIRE ON-CHIP INTERCONNECT LINES - A method for determining the layout of an interconnect line is provided including: providing a required width for the interconnect line; determining a layout of the interconnect line including slotting the interconnect line to provide two or more fingers extending along the interconnect line with an elongate slot separating adjacent fingers; and determining a number of elongate apertures to be arranged across the width of the interconnect line by comparing the required width with a maximal width for a solid metal feature, and a minimal elongate aperture width. The two or more fingers and elongate slot may be of constant width and equally spaced across the interconnect line width. The method may include selecting the number of fingers and the width of the slots to optimize the layout for a given layer technology. | 07-21-2011 |
