| Patent application number | Description | Published |
|---|
| 20090073978 | Low Latency Multicast for InfinibandR Host Channel Adapters - A low latency multicasting receive and send apparatus and method comprising low latency receive and send queues, in an InfiniBand® network each destination group of nodes (recipients) is identified by a unique Global ID (GID)+Local ID (LID). Each node whose ports are part of a multicast group identify themselves via a LID which identifies participating ports. When a switch receives such a multicast packet with a multicast LID in the packet's DLID field it replicates the packet to each of the designated ports. Each destination adapter at a receiving node receives the multicast packet and distributes copies of the packet to QPs in the host system that are registered for the multicast address. | 03-19-2009 |
| 20090073999 | Adaptive Low Latency Receive Queues - A receive queue provided in a computer system holds work completion information and message data together. An InfiniBand hardware adapter sends a single CQE+message data to the computer system that includes the completion information and data. This information is sufficient for the computer system to receive and process the data message, thereby providing a highly scalable low latency receiving mechanism. | 03-19-2009 |
| 20090077268 | Low Latency Multicast for Infiniband Host Channel Adapters - A low latency multicasting receive and send apparatus and method comprising low latency receive and send queues. In an InfiniBand® network each destination group of nodes (recipients) is identified by a unique Global ID (GID)+Local ID (LID). Each node whose ports are part of a multicast group identify themselves via a LID which identifies participating ports. When a switch receives such a multicast packet with a multicast LID in the packet's DLID field it replicates the packet to each of the designated ports. Each destination adapter at a receiving node receives the multicast packet and distributes copies of the packet to QPs in the host system that are registered for the multicast address. | 03-19-2009 |
| 20090077567 | Adaptive Low Latency Receive Queues - A receive queue provided in a computer system holds work completion information and message data together. An InfiniBand hardware adapter sends a single CQE+ message data to the computer system that includes the completion Information and data. This information is sufficient for the computer system to receive and process the data message, thereby providing a highly scalable low latency receiving mechanism. | 03-19-2009 |
| 20090213861 | Reliable Link Layer Packet Retry - Communication over a computer network with a node having a first port with a point-to-point link connection to a second node having a second port. The first port transmits to the second port a reliable link layer (RLL) packet over the link. The RLL packet comprises a first RLL header and a first data packet, the first RLL header preceding the first data packet, the first RLL header comprising an RLL start-of-frame (SOF) character and an RLL packet sequence number (PSN). If the first port receives an RLL acknowledgment control packet from the link, it acknowledges receipt of the first data packet, and the first port does not retain the first data packet in the buffer. If the first port does not receive the RLL acknowledgment packet from the link, acknowledging receipt of the first data packet, the first port re-transmits from the buffer the first data packet. | 08-27-2009 |
| 20090234974 | PERFORMANCE COUNTERS FOR VIRTUALIZED NETWORK INTERFACES OF COMMUNICATIONS NETWORKS - Performance counters are provided for virtualized network interfaces of communications networks, while minimizing the use of hardware resources. A virtualized network interface includes physical resources, as well as logical resources. Dedicated performance counters are provided for the physical resources of the virtualized network interface, as well as for logical partitions coupled to that interface, while non-dedicated performance counters are provided for the logical resources. This enables the provision of performance counters for virtualized network interfaces, while minimizing hardware resources consumed by those interfaces. | 09-17-2009 |
| 20100031272 | SYSTEM AND METHOD FOR LOOSE ORDERING WRITE COMPLETION FOR PCI EXPRESS - A method for managing the protocol of read/write messages in a PCI Express communication link is disclosed. The method comprises maintaining queues of write requests and read requests associated with each of a plurality of request identifications that are contained in a message header, wherein the read requests associated with a request identification are held in abeyance until such time that write requests associated with the request identification are completed. | 02-04-2010 |
| 20110320637 | DISCOVERY BY OPERATING SYSTEM OF INFORMATION RELATING TO ADAPTER FUNCTIONS ACCESSIBLE TO THE OPERATING SYSTEM - A tiered discovery capability is employed to obtain attributes regarding adapters of an I/O configuration. The first tier obtains a list of the adapter functions accessible to an operating system; the second tier obtains attributes regarding a selected adapter function of the list of adapter functions; and a third tier obtains common attributes of a group of adapter functions, the group including the selected adapter function. | 12-29-2011 |
| 20110320638 | ENABLE/DISABLE ADAPTERS OF A COMPUTING ENVIRONMENT - An adapter is enabled for use. The enabling includes assigning one or more address spaces to the adapter, based on a request. For each address space assigned to the adapter, a corresponding device table entry is assigned. When the adapter is no longer needed, it is disabled and the assigned device table entries become available. | 12-29-2011 |
| 20110320643 | MEASUREMENT FACILITY FOR ADAPTER FUNCTIONS - A measurement facility is provided for capturing and presenting fine-grained usage information for adapter functions in an input/output subsystem. Adapter specific input/output traffic is tracked on a per function basis and the results are dynamically presented to the user. This information is useful for performance tuning, load balancing and usage based charging, as examples. | 12-29-2011 |
| 20110320644 | RESIZING ADDRESS SPACES CONCURRENT TO ACCESSING THE ADDRESS SPACES - Address spaces are resized concurrent to accessing those address spaces. The size of an address space can be increased or decreased concurrent to performing read or write operations on the address space. Further, cache entries associated with an address space being decreased in size are purged. | 12-29-2011 |
| 20110320652 | CONTROLLING ACCESS BY A CONFIGURATION TO AN ADAPTER FUNCTION - Access to an input/output adapter by a configuration is controlled. For each requested access to an adapter, checks are made to determine whether the configuration is authorized to access the adapter. If it is not authorized, then access is denied. If it is authorized, but access should be temporarily blocked, then instruction execution is altered to indicate such. If access is permitted, but should be blocked for another reason (other than temporarily), then access is denied. | 12-29-2011 |
| 20110320662 | IDENTIFICATION OF TYPES OF SOURCES OF ADAPTER INTERRUPTIONS - A source identification facility is provided that enables identification of the one or more types of adapters requesting an interrupt in order to facilitate processing of the interrupt. The adapter types are accessible to the operating system and are used to tailor processing by the operating system of the interrupt. | 12-29-2011 |
| 20110320663 | CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION TO A GUEST OPERATING SYSTEM - One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An I/O adapter event notification may be routed and presented to a host or to a guest that the host is executing. To present the notification to the correct host or to the correct guest, various data structures in host and/or guest memory are used. | 12-29-2011 |
| 20110320664 | CONTROLLING A RATE AT WHICH ADAPTER INTERRUPTION REQUESTS ARE PROCESSED - The conditions under which adapter interruptions are made pending are controlled. Responsive to an interruption being presented to an operating system, subsequent interruptions are suppressed on all central processing units in the configuration. The operating system processes the interruption, including examining and processing indicators of reported events until the operating system discontinues the suppression. This enables the operating system to control the number of pending interruptions and the number of processors processing those interruptions. | 12-29-2011 |
| 20110320703 | ASSOCIATING INPUT/OUTPUT DEVICE REQUESTS WITH MEMORY ASSOCIATED WITH A LOGICAL PARTITION - An address controller includes a bit selector that receives a first portion of a requester id and selects a bit from a vector that identifies whether a requesting function is an SR-IOV device or a standard PCIe device. The controller also includes a selector coupled to the bit selector that forms an output comprised of either a second portion of the RID or a first portion of the address portion based on an input received from the selector and an address control unit that receives the first portion of the RID and the output and determines the LPAR that owns the requesting function based thereon, the address control unit providing the corrected memory request to the memory. | 12-29-2011 |
| 20110320756 | RUNTIME DETERMINATION OF TRANSLATION FORMATS FOR ADAPTER FUNCTIONS - Various address translation formats are available for use in obtaining system memory addresses for use by requestors, such as adapter functions, in accessing system memory. The particular address translation format to be used by a given requestor is pre-registered in a device table entry associated with that requestor. | 12-29-2011 |
| 20110320757 | STORE/STORE BLOCK INSTRUCTIONS FOR COMMUNICATING WITH ADAPTERS - Communication with adapters of a computing environment is facilitated. Instructions are provided that explicitly target the adapters. Information provided in an instruction is used to steer the instruction to an appropriate location within the adapter. | 12-29-2011 |
| 20110320758 | TRANSLATION OF INPUT/OUTPUT ADDRESSES TO MEMORY ADDRESSES - An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address. | 12-29-2011 |
| 20110320759 | MULTIPLE ADDRESS SPACES PER ADAPTER - A plurality of address spaces are assigned to an adapter. To select a particular address space for the adapter, a requestor identifier and address space identifier provided in a request by the adapter are used. Each address space may have a different address translation mechanism associated therewith. | 12-29-2011 |
| 20110320764 | LOAD INSTRUCTION FOR COMMUNICATING WITH ADAPTERS - Communication with adapters of a computing environment is facilitated. Instructions are provided that explicitly target the adapters. Information provided in an instruction is used to steer the instruction to an appropriate location within the adapter. | 12-29-2011 |
| 20110320772 | CONTROLLING THE SELECTIVELY SETTING OF OPERATIONAL PARAMETERS FOR AN ADAPTER - An instruction is provided to establish various operational parameters for an adapter. These parameters include adapter interruption parameters, input/output address translation parameters, resetting error indications, setting measurement parameters, and setting an interception control, as examples. The instruction specifies a function information block, which is a program representation of a device table entry used by the adapter, to be used in certain situations in establishing the parameters. A store instruction is also provided that stores the current contents of the function information block. | 12-29-2011 |
| 20110320860 | MANAGING PROCESSING ASSOCIATED WITH HARDWARE EVENTS - Detection, notification and/or processing of events, such as errors associated with adapters, are facilitated. Hardware detects an event, places one or more adapters in an error state to prevent access to/from the adapters, and notifies the operating system of the event. | 12-29-2011 |
| 20110321060 | OPERATING SYSTEM NOTIFICATION OF ACTIONS TO BE TAKEN RESPONSIVE TO ADAPTER EVENTS - Notification of hardware actions to be taken responsive to hardware events is facilitated. An operating system coupled, but external to, the hardware notifies firmware of the hardware action to be taken. | 12-29-2011 |
| 20110321061 | CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION - One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications. Each I/O adapter event notification includes the setting of one or more specific indicators in system memory and an interruption request, the first of which results in a pending I/O adapter interruption request. While a request for an I/O adapter interruption is pending, subsequent message signaled interruption requests are converted to I/O adapter event notifications, but do not result in additional requests for I/O adapter interruptions. | 12-29-2011 |
| 20110321158 | GUEST ACCESS TO ADDRESS SPACES OF ADAPTER - An authorization mechanism allows a host executing a guest operating system to grant permission for the guest to directly access an adapter function's address spaces without host intervention. This access is via instructions implemented based on the architecture of the adapter function. The host also has the capability to intervene in the execution of the instruction, if desired. | 12-29-2011 |
