Patent application number | Description | Published |
20100095286 | REGISTER REDUCTION AND LIVENESS ANALYSIS TECHNIQUES FOR PROGRAM CODE - A system and method for efficient architectural register liveness analysis and register usage reduction. A compiler within a computing system maintains a master liveness vector for each instruction in a program code and a path liveness vector for each path within a predetermined control flow graph (CFG). Predetermined required paths from an earlier compiler stage are used to find force paths, which are used to reduce the number of times a control block (CB) is processed. Upon completion of the liveness analysis, the compiler finds an instruction within the program code where a chosen register previously dead is now live. The compiler identifies allocation code paths from this instruction, wherein each path terminates at an instruction wherein the chosen register is dead for the first time in the allocation code path. The compiler subsequently replaces the chosen register with a determined dead register. | 04-15-2010 |
20100100711 | DATA PROCESSOR DEVICE AND METHODS THEREOF - A microsequencer is disclosed that controls the order in which microcode instructions are fetched from a microcode ROM. Each microcode instruction includes an execution command for execution by one or more execution units. Each microcode instruction also includes a microsequencer command to indicate the location of another microcode instruction at the microcode ROM. The microcode instruction can also include a delay field, indicating a selectable time when the associated microcode instruction is to be decoded. The delay field thereby provides more flexible control of the sequencing of microcode instructions. | 04-22-2010 |
20110055523 | EARLY BRANCH DETERMINATION - A method and apparatus for branch determination. The method includes a first command issuing within a computer processor, wherein execution of the first command by the computer processor includes evaluating one or more conditions to set one or more flags. The method further includes a second command issuing, subsequent to the first command issuing, within the computer processor, wherein execution of the second command by the computer processor includes causing the computer processor to wait until the one or more flags are set. Subsequent to the first and second commands issuing, the method includes a third command issuing within the computer processor, wherein execution of the third command by the computer processor includes performing a jump operation based on a value of at least one of the one or more flags set by the first command. | 03-03-2011 |
20110131381 | CACHE SCRATCH-PAD AND METHOD THEREFOR - An address containing data to be accessed is determined in response to executing an instruction received at a processor core of a microprocessor. During a scratch-pad mode of operation, it is determined whether a set of cache lines of a data cache is accessible based upon the memory location from which the instruction was retrieved. The address space of the data cache during scratch-pad mode can be isolated from other address spaces. | 06-02-2011 |
20110197003 | Interrupt Virtualization - In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an operation targeted to a memory location in a system memory to record the interrupt for a virtual processor within the guest, wherein the interrupt is to be delivered to the targeted virtual processor. In an embodiment, a virtual machine manager may be configured to detect that an interrupt has been recorded by the device interrupt manager for a virtual processor that is not currently executing. The virtual machine manager may be configured to schedule the virtual processor for execution on a hardware processor, or may prioritize the virtual processor for scheduling, in response to the interrupt. | 08-11-2011 |
20110197004 | Processor Configured to Virtualize Guest Local Interrupt Controller - In an embodiment, a guest interrupt control unit in a hardware processor may be configured to detect that an interrupt has been recorded in a memory location corresponding to a virtual processor, wherein the interrupt is targeted at the virtual processor. In response to the virtual processor being active on the hardware processor, the guest interrupt control unit is configured to provide the interrupt to the guest that includes the virtual processor. In an embodiment, a processor is configured to execute instructions from a guest, wherein the processor is configured to detect an instruction that accesses interrupt controller state data associated with a virtual processor in the guest, and wherein the processor is configured to access a memory location that stores interrupt controller state data corresponding to the virtual processor in response to the instruction. | 08-11-2011 |
20120005444 | MICROCODE RENAME RECLAMATION - A method of operating a processor includes reclaiming a physical register renamed as a microcode architectural register used by a microcode routine. The physical register is reclaimed according to an indicator corresponding to the microcode architectural register and indicating that a pointer to the physical register and corresponding to the microcode architectural register is an active pointer. | 01-05-2012 |
20120144119 | PROGRAMMABLE ATOMIC MEMORY USING STORED ATOMIC PROCEDURES - A processing core in a multi-processing core system is configured to execute a sequence of instructions as a single atomic memory transaction. The processing core validates that the sequence meets a set of one or more atomicity criteria, including that no instruction in the sequence instructs the processing core to access shared memory. After validating the sequence, the processing core executes the sequence as a single atomic memory transaction, such as by locking a source cache line that stores shared memory data, executing the validated sequence of instructions, storing a result of the sequence into the source cache line, and unlocking the source cache line. | 06-07-2012 |
20120144120 | PROGRAMMABLE ATOMIC MEMORY USING HARDWARE VALIDATION AGENT - A processing core in a multi-processing core system is configured to execute a sequence of instructions as an atomic memory transaction. Executing each instruction in the sequence comprises validating that the instruction meets a set of one or more atomicity criteria, including that executing the instruction does not require accessing shared memory. Executing the atomic memory transaction may comprise storing memory data from a source cache line into a target register, reading or modifying the memory data stored in the target register as part of executing the sequence, and storing a value from the target register to the source cache line. | 06-07-2012 |
20120303934 | METHOD AND APPARATUS FOR GENERATING AN ENHANCED PROCESSOR RESYNC INDICATOR SIGNAL USING HASH FUNCTIONS AND A LOAD TRACKING UNIT - A method and apparatus are described for generating a signal to resync a processor. In one embodiment, a particular load operation is picked from a load queue in the processor, and the particular load operation is completed out of order with respect to other load operations in the load queue. A load ordering block (LOB) in the processor receives a physical address of the completed load operation, and receives a probe data address that indicates an address of a requested data line. The LOB generates a signal to resync the processor when the physical address of the completed load operation matches the probe data address, (i.e., when bits, that have been set in a bit vector (e.g., Bloom filter) of the LOB by hashing the physical address of the completed load operation, match bits generated by hashing the probe data address). | 11-29-2012 |
20130275638 | Interrupt Virtualization - In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an operation targeted to a memory location in a system memory to record the interrupt for a virtual processor within the guest, wherein the interrupt is to be delivered to the targeted virtual processor. In an embodiment, a virtual machine manager may be configured to detect that an interrupt has been recorded by the device interrupt manager for a virtual processor that is not currently executing. The virtual machine manager may be configured to schedule the virtual processor for execution on a hardware processor, or may prioritize the virtual processor for scheduling, in response to the interrupt. | 10-17-2013 |
20140129776 | STORE REPLAY POLICY - A method is provided for executing a cacheable store. The method includes determining whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. The store instruction is replayed in response to determining to replay the store instruction. An apparatus is provided that includes a store queue (SQ) configurable to determine whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. Computer readable storage devices for adapting a fabrication facility to manufacture the apparatus are provided. | 05-08-2014 |
20140129794 | SPECULATIVE TABLEWALK PROMOTION - A method includes performing a speculative tablewalk. The method includes performing a tablewalk to determine an address translation for a speculative operation and determining whether the speculative operation has been upgraded to a non-speculative operation concurrently with performing the tablewalk. An apparatus is provided that includes a load-store unit to maintain execution operations. The load-store unit includes a tablewalker to perform a tablewalk and includes an input indicative of the operation being speculative or non-speculative as well as a state machine to determine actions performed during the tablewalk based on the input. The apparatus also includes a translation look-aside buffer. Computer readable storage devices for performing the methods and adapting a fabrication facility to manufacture the apparatus are provided. | 05-08-2014 |
20140129806 | LOAD/STORE PICKER - A method and apparatus for picking load or store instructions is presented. Some embodiments of the method include determining that the entry in the queue includes an instruction that is ready to be executed by the processor based on at least one instruction-based event and concurrently determining cancel conditions based on global events of the processor. Some embodiments also include selecting the instruction for execution when the cancel conditions are not satisfied. | 05-08-2014 |
20140164789 | AUTHENTICATING MICROCODE PATCHES WITH EXTERNAL ENCRYPTION ENGINE - A single or multicore processor having a separate hardware cryptographic engine (HCE) for microcode patch updates is presented. Microcode in each core is modified to utilize the HCE for patch updates. Various arrangements are presented. Memory for HCE processing can include shared L2 or L3 memory or a separate DRAM configured in the address space of each core or set of cores and the HCE. In some embodiments, the HCE may be located on a circuit card attached to an extension bus, such as a PCIe or LPC bus. | 06-12-2014 |
20140173290 | RETURN ADDRESS TRACKING MECHANISM - A processor, a method and a computer-readable storage medium for tracking a return address are provided. The processor comprises a hardware register and logic configured to receive a call instruction. The logic is further configured to, based on the call instruction, encrypt a return address, store the encrypted return address onto a first address in a stack and store the first address on the hardware register. | 06-19-2014 |
20140173293 | Hardware Based Return Pointer Encryption - A processor, a method and a computer-readable storage medium for encrypting a return address are provided. The processor comprises hardware logic configured to encrypt an instruction pointer and push the encrypted instruction pointer onto a stack. The logic is further configured to retrieve the encrypted instruction pointer from the stack, decrypt the instruction pointer and redirect execution to the decrypted instruction pointer. | 06-19-2014 |
20140181557 | METHODS AND APPARATUS RELATED TO PROCESSOR SLEEP STATES - A system includes a processor including at least a first core and a local interrupt controller associated with the first core. The first core is operable to store its architectural state prior to entering a first core sleep state, and the processor is operable to receive and implement a request for entering a system sleep state in which the first core is in the first core sleep state and the local interrupt controller is powered down and exit the system sleep state by restoring the local interrupt controller and restoring the saved architectural state of the first core. | 06-26-2014 |
20140195576 | Hardware Random Number Generator - A random number generator may include an input configured to receive a plurality of entropy bits generated by an entropy source of a random number generator, wherein the random number generator is configured to generate a plurality of random numbers; and an entropy health monitor coupled with the input, wherein the entropy health monitor is configured to perform a corrective action based on the plurality of entropy bits. | 07-10-2014 |
20140244984 | ELIGIBLE STORE MAPS FOR STORE-TO-LOAD FORWARDING - The present invention provides a method and apparatus for generating eligible store maps for store-to-load forwarding. Some embodiments of the method include generating information associated with a load instruction in a load queue. The information indicates whether one or more store instructions in a store queue is older than the load instruction and whether the store instruction(s) overlap with any younger store instructions in the store queue that are older than the load instruction. Some embodiments of the method also include determining whether to forward data associated with a store instruction to the load instruction based on the information. Some embodiments of the apparatus include a load-store unit that implements embodiments of the method. | 08-28-2014 |
20140310500 | PAGE CROSS MISALIGN BUFFER - The present application describes embodiments of a method and apparatus including a page cross misalign buffer. Some embodiments of the apparatus include a store queue for a plurality of entries configured to store information associated with store instructions. A respective entry in the store queue can store a first portion of information associated with a page crossing store instruction. Some embodiments of the apparatus also include one or more buffers configured to store a second portion of information associated with the page crossing store instruction. | 10-16-2014 |
20140310506 | ALLOCATING STORE QUEUE ENTRIES TO STORE INSTRUCTIONS FOR EARLY STORE-TO-LOAD FORWARDING - The present invention provides a method and apparatus for allocating store queue entries to store instructions for early store-to-load forwarding. Some embodiments of the method include allocating an entry in a store queue to a store instruction in response to the store instruction being dispatched and prior to receiving a translation of a virtual address to a physical address associated with the store instruction. The entry includes storage for data to be written to the physical address by the store instruction. | 10-16-2014 |
20140317357 | PROMOTING TRANSACTIONS HITTING CRITICAL BEAT OF CACHE LINE LOAD REQUESTS - A processor includes a cache memory, a first core including an instruction execution unit, and a memory bus coupling the cache memory to the first core. The memory bus is operable to receive a first portion of a cache line of data for the cache memory, the first core is operable to identify a plurality of data requests targeting the cache line and the first portion and select one of the identified plurality of data requests for execution, and the memory bus is operable to forward the first portion to the instruction execution unit and to the cache memory in parallel. | 10-23-2014 |