| Patent application number | Description | Published |
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| 20090221621 | Methods of Reducing Alcohol-Induced Dose Dumping for Opioid Sustained Release Oral Dosage Forms - Disclosed are methods of sustained release administration of opioids, including but not limited to hydromorphone and oxycodone, that exhibit improved properties with respect to co-ingestion with aqueous alcohol. | 09-03-2009 |
| 20100143486 | POLYETHYLENE GLYCOL-COATED SODIUM CARBONATE AS A PHARMACEUTICAL EXCIPIENT AND COMPOSITIONS PRODUCED FROM THE SAME - Non-effervescent pharmaceutical compositions having at least one particle of carbonate coated by a layer of polyethylene glycol that substantially covers the at least one carbonate particle are described. Compositions are also described where the compositions include a weakly basic therapeutic agent, a first pH-modifying agent having at least one particle of carbonate coated by a layer of polyethylene glycol, and a second pH-modifying agent. The weakly basic therapeutic agent could, but is not limited to, be zolpidem or scopolamine. Compositions including zolpidem and scopolamine are used to treat insomnia and depression, respectively. | 06-10-2010 |
| 20100266682 | POLYETHYLENE GLYCOL-COATED SODIUM CARBONATE AS A PHARMACEUTICAL EXCIPIENT AND COMPOSITIONS PRODUCED FROM THE SAME - Non-effervescent pharmaceutical compositions having at least one particle of carbonate coated by a layer of polyethylene glycol that substantially covers the at least one carbonate particle are described. Compositions are also described where the compositions include a weakly basic therapeutic agent, a first pH-modifying agent having at least one particle of carbonate coated by a layer of polyethylene glycol, and a second pH-modifying agent. The weakly basic therapeutic agent could be, but is not limited to, zolpidem or scopolamine. Compositions including zolpidem and scopolamine are used to treat insomnia and depression, respectively. | 10-21-2010 |
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| 20080249497 | Osmotically-driven fluid dispenser - Improvements in a mini-osmotic pump and coating compositions are described. The dispensing pump includes an inner fluid-filled bag encased by an osmotic layer and outer, semi-permeable membrane. The inner bag is formed with an arcuate edge at the open end of the bag to inhibit formation of fissures in the outer membrane in this edge region. The coating compositions include cellulose acetate butyrate, cellulose acetate propionate, and polymethylmethacrylate polymers, optionally mixed with ethyl cellulose in acetone based solvent systems. | 10-09-2008 |
| 20090202631 | METHODS AND DOSAGE FORMS FOR CONTROLLED DELIVERY OF PALIPERIDONE AND RISPERIDONE - Dosage forms and methods for providing a substantially ascending rate of release of paliperidone or risperidone are provided. The sustained release dosage forms provide therapeutically effective average steady-state plasma paliperidone or risperidone concentrations when administered once per day. This once-a-day dosing regimen results in only one peak plasma paliperidone or risperidone concentration occurrence in each 24 hour period. In addition, the peak plasma paliperidone or risperidone concentration occurs at a later time following dose administration and exhibits a lesser magnitude than the peak plasma paliperidone or risperidone concentration that occurs following administration of paliperidone or risperidone in an immediate-release dosage form. | 08-13-2009 |
| 20110195981 | METHODS AND DOSAGE FORMS FOR REDUCING SIDE EFFECTS OF BENZISOZAZOLE DERIVATIVES - Disclosed are dosage forms and methods comprising benzisoxazole derivatives. More particularly, disclosed are dosage forms, methods, and new uses of benzisoxazole derivatives that substantially reduce or substantially eliminate certain side effects of the benzisoxazole derivatives when dosed to a patient. | 08-11-2011 |
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| 20090016140 | DYNAMIC VOLTAGE ADJUSTMENT FOR MEMORY - A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit. | 01-15-2009 |
| 20090021989 | PROGRAMMABLE BIAS FOR A MEMORY ARRAY - A method determines a body bias for a memory cell. A supply voltage is applied to the memory cell and a bit line is precharged to a voltage lower than the supply voltage. A programmable bias voltage circuit provides a bias voltage to the memory cell in response to values on its input. Initial test values for the input are used. The memory cell is tested to determine a pass or a fail condition of the memory cell. The initial values are retained as the input values if the memory cell passes. If the memory cell fails, the memory cell is tested at changed values for the input. If the changed input values result in the memory cell being in a pass condition, the programmable bias voltage circuit is configured, in non-volatile fashion, to have the changed input values. | 01-22-2009 |
| 20090242994 | HYBRID TRANSISTOR BASED POWER GATING SWITCH CIRCUIT AND METHOD - A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth. The second source/drain extension depth is greater than the first source/drain extension depth. The second gate dielectric thickness is greater than the first gate dielectric thickness. The first transistor is used in a logic circuit. The third transistor is used in an I/O circuit. The second transistor is made without extra processing steps and is better than either the first or third transistor for coupling a power supply terminal to the logic circuit in a power-up mode and decoupling the power supply terminal from the logic circuit in a power-down mode. | 10-01-2009 |
