Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Dastidar
Jaideep Dastidar, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100228943 | ACCESS MANAGEMENT TECHNIQUE FOR STORAGE-EFFICIENT MAPPING BETWEEN IDENTIFIER DOMAINS - Access management techniques have been developed to specify and facilitate mappings between I/O and host domains in ways that are storage-efficient and which can provide flexibility in the form, granularity and/or extent of mappings, attributes and access controls coded relative to a particular I/O domain. Indeed, different identifier and/or operation translation models may be employed on a per logical device (or even a per sub-window) basis. In general, the flexibility and efficiency afforded using some embodiments of the present invention can be desirable, particularly as numbers of I/O domains increase, such as in the case of virtualization system implementations in which a multiplicity of logical I/O devices may be represented using underlying physical resources. | 09-09-2010 |
| 20100228945 | ACCESS MANAGEMENT TECHNIQUE WITH OPERATION TRANSLATION CAPABILITY - Access management techniques have been developed to specify and facilitate mappings between I/O and host domains in ways that provide flexibility in the form, granularity and/or extent of mappings, attributes and access controls coded relative to a particular I/O domain. In some embodiments of the present invention, operation translations coded relative to a particular logical I/O device, domain or sub-window seek to optimize functionality, isolation or some other figure of merit without regard to needs or limitations of another. In this way, operation translations need not be uniform and need not reduce supported operation semantics to correspond to that of a lowest common denominator I/O device. In some embodiments, the form of mappings (e.g., of operation translations) may be specialized on a per-logical-device basis (or even a per-sub-window basis), thereby offering individual logical I/O devices (or sub-windows thereof) immediate, indexed, and/or untranslated operation mapping frameworks appropriate to their individual requirements or needs. In general, flexibilities and efficiencies afforded in some embodiments of the present invention can be desirable, particularly as the diversity of I/O device types and richness of transaction semantics supported in interconnect fabrics increase. Some embodiments may be leveraged in support of sophisticated system partitions or I/O virtualizations. | 09-09-2010 |
| 20100325327 | PROGRAMMABLE ARBITRATION DEVICE AND METHOD THEREFOR - A system includes a plurality of sources to provide information access requests. An arbiter includes an assignment module to associate a first access request from the first source to one of the plurality of arbitration slots based upon assignment information at a storage location, and a dispatch module to determine one request of a plurality of requests received at the plurality of sources to be dispatched to a resource, memory controller by a dispatch module. | 12-23-2010 |
Sudipta Ghosh Dastidar, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20090246529 | Particle with Bipolar Topospecific Characteristics and Process for Preparation Thereof - A particle with bipolar topospecific characteristics, whose precursor is an asymmetric 1:1 or 2:1:1 clay particle having alternating tetrahedral and octahedral sheets terminating with a tetrahedral sheet at one external surface plane and an octahedral sheet at another external surface plane, wherein a chemical group, having greater than 3 carbon atoms, and selected from an organyl or an organoheteryl chemical group, is attached to coordinating cations on the exterior side of one of the surface sheets. | 10-01-2009 |
| 20110021799 | PARTICLE WITH BIPOLAR TOPOSPECIFIC CHARACTERISTICS AND PROCESS FOR PREPARATION THEREOF - This invention relates to particles with bipolar topospecific characteristics and process of preparation thereof. It is an object of the present invention is to provide a particle with bipolar topospecific characteristics with two spatially distinct regions on its surface having non-identical surface characteristics. It has been found that particles prepared by topospecific treatment of an asymmetric clay precursor with an organyl or an organoheteryl group attached to coordinating cations of one of the surface sheets, provides a particle with bipolar topospecific characteristics with two spatially distinct regions on its surface having non-identical surface characteristics. | 01-27-2011 |
Sunada G. Dastidar, Delhi IN
| Patent application number | Description | Published |
|---|---|---|
| 20110130403 | PYRAZOLO [3, 4-B] PYRIDINE DERIVATIVES AS PHOSPHODIESTERASE INHIBITORS - The present invention relates to phosphodiesterase (PDE) type 4, phosphodiesterase (PDE) type 7 and dual PDE type 4/PDE type 7 inhibitors. Compounds disclosed hereinf having the structure of Formula I: can be useful in the treatment, prevention, inhibition or suppression of CNS diseases, for example, multiple sclerosis; various pathological conditions such as diseases affecting the immune system, including AIDS, rejection of transplant, auto-immune disorders such as T-cell related diseases, for example, rheumatoid arthritis; inflammatory diseases such as respiratory inflammation diseases including chronic obstructive pulmonary disease (COPD), asthma, bronchitis, allergic rhinitis, adult respiratory distress syndrome (ARDS) and other inflammatory diseases including but not limited to psoriasis, shock, atopic dermatitis, eosinophilic granuloma, allergic conjunctivitis, osteoarthritis; gastrointestinal inflammation diseases such as Crohn's disease, colitis, pancreatitis as well as different types of cancers including leukaemia; especially in humans. Processes for the preparation of disclosed compounds, pharmaceutical compositions containing the disclosed compounds and their use as PDE type 4, PDE type 7 and dual PDE t e 4/PDE t e 7 inhibitors are rovided. | 06-02-2011 |
Sunanda Ghose Dastidar, New Delhi IN
| Patent application number | Description | Published |
|---|---|---|
| 20090306129 | SUBSTITUTED PYRAZOLO [3,4-B] PYRIDINES AS PHOSPHODIESTERASE INHIBITORS - The present invention relates to phosphodiesterase (PDE) type IV selective inhibitors. Processes for the preparation of disclosed compounds, pharmaceutical compositions containing the disclosed compounds and their use as PDE type IV selective inhibitors are provided. Prepared compounds correspond to structure XIV Formula (XIV). | 12-10-2009 |
| 20100022571 | SUBSTITUTED PYRAZOLO [3,4-B]PYRIDINES AS PHOSPHODIESTERASE INHIBITORS - The present invention relates to phosphodiesterase (PDE) type IV selective inhibitors. Processes for the preparation of disclosed compounds, pharmaceutical compositions containing the disclosed compounds and their use as PDE type IV selective inhibitors are provided. Prepared compounds correspond to structure XIV. | 01-28-2010 |
Sunanda Ghosh Dastidar, Delhi IN
| Patent application number | Description | Published |
|---|---|---|
| 20080280926 | Phosphodiesterase Inhibitors - The present invention relates to purine derivatives, which can be used as selective phosphodiesterase (PDE) type IV inhibitors. Compounds disclosed herein can be useful in the treatment of asthma, arthritis, bronchitis, chronic obstructive pulmonary disease (COPD), psoriasis, allergic rhinitis, shock, atopic dermatitis, Crohn's disease, adult respiratory distress syndrome (ARDS), eosinophilic granuloma, allergic conjunctivitis, osteoarthritis, ulcerative colitis and other inflammatory diseases especially in humans. Also provided are processes for the preparation of disclosed compounds, pharmaceutical composition containing the disclosed compounds and their use as selective phosphodiesterase (PDE) type IV inhibitors. | 11-13-2008 |
Sunanda Ghosh Dastidar, New Delhi IN
| Patent application number | Description | Published |
|---|---|---|
| 20080207659 | INHIBITORS OF PHOSPHODIESTERASE TYPE 4 - The present invention relates to inhibitors of phosphodiesterase (PDE) type 4. | 08-28-2008 |
Tathagato Rai Dastidar, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20090300558 | USE OF STATE NODES FOR EFFICIENT SIMULATION OF LARGE DIGITAL CIRCUITS AT THE TRANSISTOR LEVEL - A method is provided for simulating a sequential digital circuit module given a set of input conditions and a current state for the circuit. The method comprises initiating all state nodes of the circuit module to logic values stored in the current state, initializing all sequential submodules of the circuit module to the states stored in the current state, simulating the circuit module after initialization, and after completion of the simulation step, reporting the output logic values and associated delays and storing the logic values of the state nodes and the states of the sequential modules in the next state in the circuit module, multiple value changes in the state nodes of the circuit module being recorded on the next state. | 12-03-2009 |