Patent application number | Description | Published |
20130082851 | COMPRESSION FORMAT FOR HIGH BANDWIDTH DICTIONARY COMPRESSION - Method, apparatus, and systems employing dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead. | 04-04-2013 |
20130086339 | METHOD AND APPARATUS FOR HIGH BANDWIDTH DICTIONARY COMPRESSION TECHNIQUE USING DELAYED DICTIONARY UPDATE - Method, apparatus, and systems employing novel delayed dictionary update schemes for dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead. | 04-04-2013 |
20130091317 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 04-11-2013 |
20130097353 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 04-18-2013 |
20130111086 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS | 05-02-2013 |
20130132622 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-23-2013 |
20130132636 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-23-2013 |
20130132683 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-23-2013 |
20130205055 | METHOD AND APPARATUS FOR HIGH BANDWIDTH DICTIONARY COMPRESSION TECHNIQUE USING SET UPDATE DICTIONARY UPDATE POLICY - Method, apparatus, and systems employing novel dictionary entry replacement schemes for dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead. | 08-08-2013 |
20140006677 | EMBEDDED CONTROL CHANNEL FOR HIGH SPEED SERIAL INTERCONNECT | 01-02-2014 |
20140095751 | FAST DESKEW WHEN EXITING LOW-POWER PARTIAL-WIDTH HIGH SPEED LINK STATE - Methods and apparatus relating to fast deskew when exiting a low-power partial-width high speed link state are described. In one embodiment, an exit flit on active lanes and/or a wake signal/sequence on idle lanes may be transmitted at a first point in time to cause one or more idle lanes of a link to enter an active state. At a second point in time (following or otherwise subsequent to the first point in time), training sequences are transmitted over the one or more idle lanes of the link. And, the one or more idle lanes are deskewed in response to the training sequences and prior to a third point in time (following or otherwise subsequent to the second point in time). Other embodiments are also disclosed and claimed. | 04-03-2014 |
20140112339 | HIGH PERFORMANCE INTERCONNECT - A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state | 04-24-2014 |
20140115207 | HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER - A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link. | 04-24-2014 |
20140176353 | COMPRESSION FORMAT FOR HIGH BANDWIDTH DICTIONARY COMPRESSION - Method, apparatus, and systems employing dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead. | 06-26-2014 |
20140189427 | LIVE ERROR RECOVERY - A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode. | 07-03-2014 |
20140281062 | APPARATUS, SYSTEM AND METHOD FOR PROVIDING ACCESS TO A DEVICE FUNCTION - Techniques and mechanisms for providing access to a function with an input/output (I/O) device. In an embodiment, a main memory of a computer system including the I/O device stores a function-context data structure associating a function with a context for an access to the function. The I/O device stores a configuration for the I/O device to provide the function. In another embodiment, the software process exchanges information with the function-context data structure for the access to the function. The I/O device performs a synchronization of the function-context data structure and the configuration data structure with respect to one another, wherein the function-context data structure operates as a register level interface which interfaces the I/O device and the software process with one another. | 09-18-2014 |
20140281067 | Apparatus, system, and method for performing link training and equalization - A system and method comprising, in response to a first component and a second component undergoing a link training and equalization procedure, a second component is to communicate a first set of data to the first component via a first transmission logic along at least one channel of a communications link. The first component and the second component are link partners. The first set of data further includes a full swing value and a low frequency value which are stored in a first storage unit of the first component. The first component is to store a first computed set of coefficients from the full swing value and the low frequency value. The second component is to apply the first computed set of coefficients to the first transmission logic of the second component. | 09-18-2014 |
20140281068 | APPARATUS, SYSTEM, AND METHOD FOR IMPROVING EQUALIZATION WITH A HARDWARE DRIVEN ALGORITHM - A system and method comprising, in response to a first component and a link partner of the first component, undergoing equalization, the first component is to communicate a first set of data to the link partner component. The first component may comprise at least one receiver to receive a first set of equalization data. The first component may further comprise coefficient storage coupled to the receiver to store the equalization data. In addition, coefficient logic coupled to the coefficient storage to generate a first set of coefficients based on the first set of equalization data. The first component is to send the first set of coefficients to the link partner component. | 09-18-2014 |
20140372658 | MULTIPLE TRANSACTION DATA FLOW CONTROL UNIT FOR HIGH-SPEED INTERCONNECT - Methods, apparatus, and systems, for transporting data units comprising multiple pieces of transaction data over high-speed interconnects. A flow control unit, called a KTI (Keizer Technology Interface) Flit, is implemented in a coherent multi-layer protocol supporting coherent memory transactions. The KTI Flit has a basic format that supports use of configurable fields to implement KTI Flits with specific formats that may be used for corresponding transactions. In one aspect, the KTI Flit may be formatted as multiple slots used to support transfer of multiple respective pieces of transaction data in a single Flit. The KTI Flit can also be configured to support various types of transactions and multiple KTI Flits may be combined into packets to support transfer of data such as cache line transfers. | 12-18-2014 |
20150067208 | HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER - A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link. | 03-05-2015 |