| Patent application number | Description | Published |
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| 20100073073 | MICROPROCESSOR WITH SUBSTRATE BIAS CLAMPS - A microprocessor including a substrate bias rail providing a bias voltage during a first operating mode, a supply node providing a core voltage, a clamp device coupled between the bias rail and the supply node, and control logic. The control logic turns on the clamp device to clamp the bias rail to the supply node during a second operating mode and turns off the clamp device during the first operating mode. The clamp devices may be implemented with P-channel and N-channel devices. Level shift and buffer circuits may be provided to control the clamp devices based on substrate bias voltage levels. The microprocessor may include a substrate with first and second areas each including separate substrate bias rails. The control logic separately turns on and off clamp devices to selectively clamp the substrate bias rails in the first and second areas based on various power modes. | 03-25-2010 |
| 20100073074 | MICROPROCESSOR WITH SELECTIVE SUBSTRATE BIASING FOR CLOCK-GATED FUNCTIONAL BLOCKS - A microprocessor according to one embodiment includes a supply node providing a core voltage, a functional block, a charge node, select logic, and substrate bias logic. The functional block has multiple power modes and includes one or more semiconductor devices and a substrate bias rail routed within the functional block and coupled to a substrate connection of at least one semiconductor device. The select logic couples the substrate bias rail to the charge node when the functional block is in a low power mode and clamps the substrate bias rail to the supply node when the functional block is in a full power mode. The substrate bias logic charges the charge node to a bias voltage at an offset voltage relative to the core voltage when the functional block is in the low power mode. Semiconductor devices may be provided to clamp or otherwise couple the bias rail. | 03-25-2010 |
| 20100229012 | MICROPROCESSOR THAT PERFORMS ADAPTIVE POWER THROTTLING - A microprocessor that performs adaptive power throttling includes a calculation unit that calculates an average power consumed by the microprocessor over a most recent predetermined sample time and determines whether the average power is less than a predetermined maximum power value. A power management unit controls the microprocessor to conditionally operate at a predetermined frequency if the average power is less than the predetermined maximum power value. The predetermined frequency is a frequency at which the microprocessor may consume more than the predetermined maximum power value. The predetermined maximum power value and sample time are specified to achieve power and/or thermal design goals of a system in which the microprocessor operates. The predetermined maximum power and/or sample time values are programmable by system software. To maintain a running average power value, a counter is incremented, both in sleeping and running states, by different increments depending upon the current performance point. | 09-09-2010 |
| 20100262729 | CONFIGURABLE BUS TERMINATION FOR MULTI-CORE/MULTI-PACKAGE PROCESSOR CONFIGURATIONS - A multi-core/multi-package bus termination apparatus includes a configuration array and a plurality of drivers. The configuration array generates location/protocol signals that each direct one of the plurality of drivers on the bus to employ location-based bus termination or protocol-based bus termination. The plurality of drivers is coupled to the plurality of location/protocol signals, a plurality of location signals, a bus ownership signal, and a multi-package signal. Each of the plurality of drivers controls how one of a plurality of nodes is driven responsive to a first state of one of the plurality of location/protocol signals. Each has configurable multi-core/multi-package logic controls pull-up logic, first pull-down logic, and second pull-down logic according to location-based termination rules if the first state indicates the location-based termination, and controls the pull-up logic, the first pull-down logic, and the second pull-down logic according to protocol-based termination rules if the first state indicates the protocol-based termination. | 10-14-2010 |
| 20100262733 | PROTOCOL-BASED BUS TERMINATION FOR MULTI-CORE PROCESSORS - A multi-core bus termination apparatus includes a protocol analyzer and a plurality of drivers. The protocol analyzer is disposed within a processor core and configured to receive one or more protocol signals, and is configured to indicate whether or not the processor core owns the bus. The plurality of drivers is coupled to the protocol analyzer. Each of the plurality of drivers has one of a corresponding plurality of nodes, and each is configured to control how the one of the corresponding plurality of nodes is driven responsive whether or not the processor core owns the bus. Each of the plurality of drivers has protocol-based multi-core logic. The protocol-based multi-core logic is configured to enable pull-up logic if the processor core owns the bus, and is configured to disable the pull-up logic if the processor core does not own the bus. | 10-14-2010 |
| 20100262747 | LOCATION-BASED BUS TERMINATION FOR MULTI-CORE PROCESSORS - A multi-core bus termination apparatus includes a location array and a plurality of drivers. The location array generates a plurality of location signals that indicate locations on the bus of a corresponding plurality of nodes that are coupled to the bus, where the locations comprise either an internal location or a bus end location. Each of the plurality of drivers has one of the corresponding plurality of nodes, and controls how the one of the corresponding plurality of nodes is driven responsive to a state of a corresponding one of the plurality of location signals. Each of the plurality of drivers has configurable multi-core logic. The configurable multi-core logic enables pull-up logic and first pull-down logic if the state indicates the bus end location. The configurable multi-core logic disables the pull-up logic and to enable the first pull-down logic and second pull-down logic if the state indicates the internal location. | 10-14-2010 |
| 20100324750 | MICROPROCESSOR WITH IMPROVED THERMAL MONITORING AND PROTECTION MECHANISM - A microprocessor including a temperature sensor that monitors a temperature of core logic of the microprocessor during operation thereof, and operating point information from which may be determined N operating points at which the microprocessor core may reliably operate at a first temperature. Each of the N operating points has a different combination of operating frequency and voltage. The N operating points comprise a highest operating point, a lowest operating point, and a plurality of operating points intermediate the highest and lowest operating points. The microprocessor also includes a control circuit that transitions operation of the core logic among the N operating points to attempt to keep the operating temperature of the core logic provided by the temperature sensor within a temperature range whose upper bound is the first temperature. | 12-23-2010 |
| 20110035616 | DETECTION OF UNCORRECTABLE RE-GROWN FUSES IN A MICROPROCESSOR - A microprocessor includes a first plurality of fuses, a predetermined number of which are selectively blown. Control values are provided from the first plurality of fuses to circuits of the microprocessor to control operation of the microprocessor. The microprocessor also includes a second plurality of fuses, blown with the predetermined number of the first plurality of fuses that are blown. In response to being reset, the microprocessor is configured to: read the first plurality of fuses and count a number of them that are blown; read the predetermined number from the second plurality of fuses; compare the counted number with the predetermined number read from the second plurality of fuses; and prevent itself from fetching and executing user program instructions if the number counted from reading the first plurality of fuses does not equal the predetermined number read from the second plurality of fuses. | 02-10-2011 |
| 20110035623 | DETECTION OF FUSE RE-GROWTH IN A MICROPROCESSOR - A microprocessor includes a first plurality of fuses, a predetermined number of which are selectively blown. Control values are provided from the fuses to circuits of the microprocessor to control operation thereof. A second plurality of fuses are blown with the predetermined number of the first plurality of fuses that are blown and a Boolean complement of the predetermined number. In response to being reset, the microprocessor: reads the predetermined number and the Boolean complement of the predetermined number from the second plurality of fuses, Boolean complements the predetermined number read from the second plurality of fuses to generate a result, compares the result with the Boolean complement of the predetermined number read from the second plurality of fuses, and prevent itself from fetching and executing user program instructions if the result does not equal the Boolean complement of the predetermined number read from the second plurality of fuses. | 02-10-2011 |
| 20110113196 | AVOIDING MEMORY ACCESS LATENCY BY RETURNING HIT-MODIFIED WHEN HOLDING NON-MODIFIED DATA - A microprocessor is configured to communicate with other agents on a system bus and includes a cache memory and a bus interface unit coupled to the cache memory and to the system bus. The bus interface unit receives from another agent coupled to the system bus a transaction to read data from a memory address, determines whether the cache memory is holding the data at the memory address in an exclusive state (or a shared state in certain configurations), and asserts a hit-modified signal on the system bus and provides the data on the system bus to the other agent when the cache memory is holding the data at the memory address in an exclusive state. Thus, the delay of an access to the system memory by the other agent is avoided. | 05-12-2011 |
