Patent application number | Description | Published |
20090014866 | MULTICHIP MODULE PACKAGE AND FABRICATION METHOD - A method for fabricating a multichip module package includes providing a first heat sink positioned for releasing heat from the package and providing a second heat sink positioned proximate the first heat sink. The heat sinks are thermally coupled and electrically isolated to and from one another. A first semiconductor device is attached to the first heat sink in thermal and electrical communication therewith and electrically insulated from the second heat sink. A second semiconductor device is attached to the second heat sink in thermal and electrical communication therewith and electrically insulated from the first heat sink. | 01-15-2009 |
20090152704 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER - An integrated circuit packaging system is provided including forming an interposer having a coupling slot, securing an upper die on the interposer, mounting the interposer over an integrated circuit, and coupling the integrated circuit to the upper die through the coupling slot. | 06-18-2009 |
20100038771 | INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE - A method of manufacturing an integrated circuit package includes: forming a substrate that includes: forming a core layer, forming vias in the core layer, and forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer. | 02-18-2010 |
20100078794 | STACKED DIE SEMICONDUCTOR DEVICE HAVING CIRCUIT TAPE - A stacked die semiconductor package includes a first integrated circuit chip, a first circuit tape coupled to the first integrated circuit chip, a second integrated circuit chip coupled to the first circuit tape, and at least one component coupled to the first circuit tape. The at least one component may include one or more passive components, one or more active components, or a combination of passive and active components. The stacked die semiconductor package can also include a second circuit tape coupled to the second integrated circuit chip and a third integrated circuit chip coupled to the second circuit tape. The stacked die semiconductor package can also include an encapsulant. | 04-01-2010 |
20100140761 | Quad Flat Package - A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package. | 06-10-2010 |
20100144100 | Method of Forming Quad Flat Package - A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package. | 06-10-2010 |
20100224991 | INTEGRATED CIRCUIT HEAT SPREADER STACKING SYSTEM - An integrated circuit heat spreader stacking system includes: an integrated circuit on a substrate; a heat spreader having a heat sink dome; a stacking stand-off for the heat spreader; and the heat spreader mounted with the heat sink dome over the integrated circuit. | 09-09-2010 |
20110001240 | Chip Scale Module Package in BGA Semiconductor Package - A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the BGA substrate, and an application die attached to the IPD. A method of manufacturing a semiconductor package includes providing a BGA substrate having integrated metal layer circuitry, attaching a flip chip CSMP having a first IPD to the BGA substrate, and attaching an application die to the IPD. | 01-06-2011 |
20120018886 | INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE AND METHOD OF MANUFACTURING THEREOF - A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer. | 01-26-2012 |