| Patent application number | Description | Published |
|---|
| 20090055589 | Cache memory system for a data processing apparatus - A data processing apparatus is provided having a cache memory | 02-26-2009 |
| 20090100054 | Adaptive comparison control in a data store - Data store access circuitry is disclosed that comprises: a data store for storing values; comparator circuitry coupled to said data store and responsive to receipt of a data access request comprising an address to compare at least a portion of said address with at least a portion of one or more of said values stored in said data store so as to identify a stored value matching said address; a base value register coupled to said comparator circuitry and storing a base value corresponding to at least a portion of at least one of said stored values; and comparator control circuitry coupled to said comparator circuitry to control: (i) which portion of said address is processed as a non-shared portion and compared by said comparator circuitry with non-shared portions of said one or more stored values stored in said data store; and (ii) which portion of said address is processed as a shared portion and compared by said comparator circuitry with a shared portion of said base value stored in said base value register; wherein said shared portion of said base value has a value matching corresponding portions of all of said stored values stored within said data store. | 04-16-2009 |
| 20090157985 | Accessing memory arrays - A memory controller for controlling access to a memory, said memory comprising at least one memory array, said at least one memory array comprising a plurality of rows and a plurality of columns, access to an element within said memory array being performed by opening a row comprising said element and then accessing a column comprising said element, said at least one memory array being adapted to have no more than one row in said at least one memory array open at a time; said memory controller being responsive to a memory access request to access an element within said memory and following said access to determine if said row comprising said accessed element should be closed or should remain open in dependence upon a property of said memory access request. | 06-18-2009 |
| 20090164998 | Management of speculative transactions - Circuitry for receiving transaction requests from a plurality of masters and the masters themselves are disclosed. The circuitry comprises: an input port for receiving said transaction requests, at least one of said transaction requests received comprising an indicator indicating if said transaction is a speculative transaction; an output port for outputting a response to said master said transaction request was received from; and transaction control circuitry; wherein said transaction control circuitry is responsive to a speculative transaction request to determine a state of at least a portion of a data processing apparatus said circuitry is operating within and in response to said state being a predetermined state said transaction control circuitry generates a transaction cancel indicator and outputs said transaction cancel indicator as said response, said transaction cancel indicator indicating to said master that said speculative transaction will not be performed. | 06-25-2009 |
| 20090271583 | Monitoring transactions in a data processing apparatus - Apparatus for processing data is provided comprising processing circuitry and monitoring circuitry for monitoring write transactions and performing transaction authorisations of certain transactions in dependence upon associated memory addresses. The processing circuitry is configured to enable execution of a write instruction corresponding to a write transaction to be monitored to continue to completion whilst the monitoring circuitry is performing monitoring of the write transactions and the monitoring circuitry is arranged to cause storage of write transaction data in an intermediate storage element for those transactions for which an authorisation is required. Storage of write transaction data in an intermediate storage element enables the write transaction to be reissued in dependence upon the result of the transaction authorisation although the corresponding write instruction has already completed. | 10-29-2009 |
| 20100177105 | METHODS OF AND APPARATUS FOR PROCESSING GRAPHICS - In a tile-based graphics processor, primitive lists (bins) are prepared for 2×2 blocks of tiles | 07-15-2010 |
| 20110074765 | Graphics processing system - A transaction elimination hardware unit | 03-31-2011 |
| 20110074800 | Method and apparatus for controlling display operations - A graphics processing system includes a graphics processor | 03-31-2011 |
| 20110080419 | Methods of and apparatus for controlling the reading of arrays of data from memory - A display controller reads blocks of data from a frame buffer and stores them in a local memory buffer of the display controller before outputting the blocks of data to a display. The display controller uses similarity meta-data associated with the output frame in the frame buffer to determine whether a new block of data to be processed for display is similar to a block of data already stored in the local memory of the display controller or not. If it is determined that the data block to be processed is similar to a data block already stored in the local buffer of the display controller, the display controller does not read a new data block from the frame buffer but instead provides the existing data block in its buffer to the display. | 04-07-2011 |
| 20110102446 | Graphics processing systems - A graphics processor | 05-05-2011 |
