| Patent application number | Description | Published |
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| 20080222388 | Simulation of processor status flags - The dynamic efficient and accurate simulation of processor status flags is described. One exemplary embodiment includes simulation of processor status flags of a first CPU type on a second CPU type using simple arithmetic operations to calculate status flags in parallel, and by keeping an intermediate state that allows efficient calculation of status flags when they are needed. In this way, sufficient intermediate state exists to generate desired status flags either directly or with a simple operation. | 09-11-2008 |
| 20090006750 | Leveraging transactional memory hardware to accelerate virtualization and emulation - Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. State isolation can be facilitated by providing isolated private state on transactional memory hardware and storing the stack of a host that is performing an emulation in the isolated private state. Memory accesses performed by a central processing unit can be monitored by software to detect that a guest being emulated has made a self modification to its own code sequence. Transactional memory hardware can be used to facilitate dispatch table updates in multithreaded environments by taking advantage of the atomic commit feature. An emulator is provided that uses a dispatch table stored in main memory to convert a guest program counter into a host program counter. The dispatch table is accessed to see if the dispatch table contains a particular host program counter for a particular guest program counter. | 01-01-2009 |
| 20090006751 | Leveraging transactional memory hardware to accelerate virtualization and emulation - Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. A central processing unit is provided with the transactional memory hardware. Code backpatching can be facilitated by providing transactional memory hardware that supports a facility to maintain private memory state and an atomic commit feature. Changes made to certain code are stored in the private state facility. Backpatching changes are enacted by attempting to commit all the changes to memory at once using the atomic commit feature. An efficient call return stack can be provided by using transactional memory hardware. A call return cache stored in the private state facility captures a host address to return to after execution of a guest function completes. A direct-lookup hardware-based hash table is used for the call return cache. | 01-01-2009 |
| 20090007107 | Leveraging transactional memory hardware to accelerate virtualization emulation - Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. One or more central processing units are provided with transactional memory hardware that is operable to accelerate virtualization. The transactional memory hardware has a facility to maintain private state, a facility to render memory accesses from other central processing units visible to software, and support for atomic commit of the private state. The transactional memory hardware can be used, for example, to facilitate emulation of precise exception semantics. The private state is operable to enable an emulated state to remain inconsistent with an architectural state and only synchronized on certain boundaries. An optimized sequence of instructions is executed using chunk-accurate simulation to try and achieve a same end effect. | 01-01-2009 |
| 20090030668 | SIGNED/UNSIGNED INTEGER GUEST COMPARE INSTRUCTIONS USING UNSIGNED HOST COMPARE INSTRUCTIONS FOR PRECISE ARCHITECTURE EMULATION - Architecture for efficient translation and processing of PowerPC guest instructions on an x86 host machine. In an x86-based architecture, signed integer values are projected into the unsigned integer value space for processing by the host using the negation of the left-most (sign) bit. Compare operations are performed in the unsigned space and the compare results are written into the host flags register. Once the compare results are written into the host flags register, the flag values can be read out and used in a table lookup to retrieve the corresponding values for the guest register. The guest flag values are then passed into the guest flags register for processing by the guest application. | 01-29-2009 |
| Patent application number | Description | Published |
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| 20080281987 | FACILITATING AUTOMATIC PROTECTION SWITCHING FOR PROVIDER BACKBONE NETWORK - An existing protection mechanism is enhanced through the use of an automatic protection switching protocol data unit (APS PDU). In conjunction with transmitting Ethernet frames to a second bridge over a primary path, a first bridge transmits APS PDUs to the second bridge over a secondary path. The APS PDUs provide the second bridge with information about the protection switching mechanism being used and provide indications regarding the status of the primary path. In particular, protection switching may be facilitated by forming an APS PDU that is extended to include an indication of an identity for a trunk or a primary path before transmitting the APS PDU to the second bridge. Alternatively, after forming a regular APS PDU, protection switching may be facilitated by encapsulating the regular APS PDU with information identifying a trunk or a primary path before transmitting the APS PDU to the second bridge. | 11-13-2008 |
| 20100074101 | Distributed Connection Establishment and Restoration - Connection constraints are flooded using an extension to a routing protocol being used to control forwarding on network. Nodes maintain topology and connection database and calculate routes for connections based on the constraints. If a node is on a calculated route for a connection it will install forwarding state for the connection. Since each node has a consistent view of the network topology and has been provided with the constraints associated with the connection, each node on the network will calculate the same route for the connection. When a failure occurs, the nodes will calculate restoration paths for the connections on a network-wide priority basis to enable restoration paths to be created for the affected connections without requiring the restoration paths to be signaled. Time-stamps are used to allow events to be applied by nodes in a consistent order regardless of the order in which they arrive. | 03-25-2010 |
| 20100118878 | METHOD AND APPARATUS FOR NON-DISRUPTIVE CALL MODIFICATION - A method and system for changing the extent of data plane resources controlled by a control plane for a network connection which spans a contiguous set of nodes controlled by existing network control resources is disclosed. This is done in a non-disruptive manner. This typically involves two steps: i) Creating a new set of control plane resources for said network connection such that said data plane resources are shared with said existing network control resources; and ii) then terminating the existing network control resources such that said data plane resources are fully transferred to the new set of control plane resources without disrupting said network connection. The existing network control resources can be either a control plane resource or a non control plane resource. An example of a non control plane resource is network management software (e.g., an OSS (Operation Support System)), which forms part of the Management Plane. It should be noted that this does not need to be done for a complete end-to-end connection, but rather can be executed for the portion of the end-to-end connection which is to be controlled by the control plane. | 05-13-2010 |
