| Patent application number | Description | Published |
|---|
| 20080216950 | ADHESIVE WITH DIFFERENTIAL OPTICAL PROPERTIES AND ITS APPLICATION FOR SUBSTRATE PROCESSING - An adhesive adapted with particular optical properties, and its use to couple a substrate to a substrate holder during substrate processing are disclosed. After processing the substrate, the optical properties of the adhesive may be exploited to locate and/or remove adhesive residue that may be present on the substrate. | 09-11-2008 |
| 20080265407 | WAFER-LEVEL BONDING FOR MECHANICALLY REINFORCED ULTRA-THIN DIE - An embodiment of the present invention is a technique to fabricate a package. A metal sheet having trenches is formed. A thinned wafer supported by a wafer support substrate (WSS) is formed. The metal sheet is bonded to the WSS-supported thinned wafer to form a metal bonded thinned wafer. The thinned wafer is diced to the trenches into die assemblies. | 10-30-2008 |
| 20080277781 | MULTI-DIE MOLDED SUBSTRATE INTEGRATED CIRCUIT DEVICE - One embodiment includes a substrate having a plurality of dies and a support frame made of molding material which is molded between adjacent dies so as to join together and support adjacent dies. The embodiment further has a plurality of interconnects formed on selected die terminals and the molding material of the support frame joining adjacent dies. The interconnects may be formed utilizing a variety of techniques including those of the type used in conventional wafer fabrication techniques. Other embodiments are described and claimed. | 11-13-2008 |
| 20080316662 | Reducing input capacitance for high speed integrated circuits - An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity if formed underneath the pad. Other embodiments are described and claimed. | 12-25-2008 |
| 20090001556 | LOW TEMPERATURE THERMAL INTERFACE MATERIALS - A method may provide thermal interface material. The method comprises providing a first coating layer on a top side of a base metal layer and a second coating layer on a bottom side of the base metal layer, wherein the coating layer has a melting point lower than a melting point of the base metal layer; attaching the base metal layer to a die and a heat spreader; and melting the first coating layer and the second coating layer to bond to the die and the heat spreader. | 01-01-2009 |
| 20090034206 | WAFER-LEVEL ASSEMBLY OF HEAT SPREADERS FOR DUAL IHS PACKAGES - An embodiment of the present invention is a technique to fabricate a package. A heat spreader (HS) array on a HS support substrate is formed. The HS array has a plurality of heat spreaders. A diced wafer supported by a wafer support substrate (WSS) is formed. The diced wafer has a plurality of thin dice. The thin dice in the diced wafer are bonded to the heat spreaders in the HS array to form HS-bonded thin dice between the HS support substrate and the WSS. | 02-05-2009 |
| 20090074350 | Electrically pluggable optical interconnect - An optical interconnect is provided which may allow flexible high-bandwidth interconnection between chips, eliminate the need for optical alignment between the optoelectrical (OE) die and waveguide during assembly because the OE die is at least partially embedded inside the waveguide (lower cladding layer, upper cladding layer, and core layer), eliminate the need for handling the optical interconnect at OEM, and not impact current substrate and motherboard technology | 03-19-2009 |
| 20090079064 | METHODS OF FORMING A THIN TIM CORELESS HIGH DENSITY BUMP-LESS PACKAGE AND STRUCTURES FORMED THEREBY - Methods of forming microelectronic device structures are described. Those methods may include placing a plurality of support rings onto a tacky layer of a support carrier, wherein the support rings are disposed within a cavity of the support carrier; placing a plurality of thin die onto a pedestal of the support carrier, wherein a top surface of the thin die is substantially flush with at top surface of the support ring; and then building up layers on the top surface of the die. | 03-26-2009 |
| 20090085228 | DIE WARPAGE CONTROL - A semiconductor package comprises a substrate; a semiconductor die that comprises a set of one or more interconnects on one side to couple to the substrate; and a shape memory alloy layer provided on another side of the semiconductor die to compensate warpage of the semiconductor die. The shape memory alloy layer deforms with warpage of the semiconductor die and changes from the deformed shape to an original shape to flatten the semiconductor die in response to rise of a temperature during coupling of the die to the substrate. | 04-02-2009 |
| 20090087949 | Method of Making a Microelectronic Package Using an IHS Stiffener - A method of making a microelectronic package. The method includes: providing a carrier; providing a tacky pad on the carrier; placing a die onto the tacky pad such that an active surface of the die adheres to the tacky pad, bonding an IHS onto a backside of the die after placing to form a die-IHS combination, removing the die-IHS combination from the tacky pad; and mounting the die-IHS combination onto a package substrate to form the package. | 04-02-2009 |
| 20090129422 | HIGH-VOLUME ON-WAFER HETEROGENEOUS PACKAGING OF OPTICAL INTERCONNECTS - An optical connector module complete with optoelectronic devices supporting integrated circuitry, and connector housing may be fabricated on a wafer level. A plurality of cavities may be formed on the backside of the wafer to accommodate an optoelectronic device. Active circuitry may be formed in a front side of the wafer. Through-vias electrically connect the front side to the back side. The backside of the wafer is overmolded with a polymer layer which when singulated into individual dies forms the plastic housing of an optical connector module. | 05-21-2009 |
| 20090162005 | Wafer based optical interconnect - In general, in one aspect, a method includes forming conductive layers on a wafer. A through cavity is formed in alignment with the conductive layers. The through cavity is to permit an optical signal from an optical waveguide within an optical connector to pass therethrough. Alignment holes are formed on each side of the through cavity to receive alignment pins. The wafer having the conductive layers, the through cavity in alignment with the conductive layers, and the alignment holes on each side of the through cavity forms an optical-electrical (O/E) interface. An O/E converter is mounted to the metal layers in alignment with the through cavity. The alignment pins and the alignment holes are used to passively align the optical waveguide and the O/E converter. | 06-25-2009 |
| 20090200681 | Forming Compliant Contact Pads For Semiconductor Packages - In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed. | 08-13-2009 |
| 20090201643 | INTEGRATED MICRO-CHANNELS FOR 3D THROUGH SILICON ARCHITECTURES - Some embodiments of the present invention include apparatuses and methods relating to integrated micro-channels for removing heat from 3D through silicon architectures. | 08-13-2009 |
| 20090244873 | OPTICAL PACKAGE - A method for aligning at least two photonic components over an interposer, and an optical package that may align such components. The method may include providing an interposer; fabricating electrical conductors passing from one surface of the interposer to an opposite surface of the interposer at selected contact positions; soldering the photonic components over the selected contact positions on the first surface, while allowing solder self-alignment. Other embodiments are described and claimed. | 10-01-2009 |
| 20090250707 | Multi-chip assembly with optically coupled die - Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed. | 10-08-2009 |
| 20100246138 | METHOD, APPARATUS, AND SYSTEM FOR THIN DIE THIN THERMAL INTERFACE MATERIAL IN INTEGRATED CIRCUIT PACKAGES - Some embodiments of the invention include a thermal interface between a heat spreader and a die. The thermal interface may include a main layer of a single material or a combination of multiple materials. The thermal interface may include one or more additional layers covering one or more surfaces of the main layer. The thermal interface may be bonded to the die and the heat spreader at a low temperature, with flux or without flux. Other embodiments are described and claimed. | 09-30-2010 |
| 20110058419 | MULTI-CHIP ASSEMBLY WITH OPTICALLY COUPLED DIE - Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed. | 03-10-2011 |
| 20110059596 | SEMICONDUCTOR WAFER COAT LAYERS AND METHODS THEREFOR - Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability. | 03-10-2011 |
