Patent application number | Description | Published |
20110037524 | OSCILLATOR AMPLIFIER WITH INPUT CLOCK DETECTION AND METHOD THEREFOR - An oscillator circuit has a crystal oscillator amplifier having only two clock input terminals, one being an input terminal and the other being an output terminal. The input terminal allows a user of the integrated circuit to choose between connecting a first clock signal generated from a crystal or a second clock signal generated by a non-crystal source to the input terminal. Control circuitry has a capacitor coupled in parallel with a transistor. Both are coupled in series with a resistive device at an output of the control circuitry to provide a control signal. Clock generation circuitry coupled to the crystal oscillator amplifier provides an oscillating output signal in response to an enable signal. In one form a comparator circuit provides the oscillating output signal. The control signal is used to ensure that inputs to the comparator circuit repeatedly cross each other over time. | 02-17-2011 |
20110185212 | DATA PROCESSING SYSTEM HAVING BROWN-OUT DETECTION CIRCUIT - A brown-out detection circuit comprises a first resistive element, a first transistor, a second transistor, and a comparator. The first resistive element has a first terminal coupled to a first power supply voltage terminal, and a second terminal. The first transistor is of a first conductivity type and has a first current electrode coupled to the second terminal of the first resistive element, a control electrode, and a second current electrode. The second transistor is of a second conductivity type and has a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode coupled to a second power supply voltage terminal. The comparator has a first input terminal coupled to the first terminal of the first resistive element, a second input terminal coupled to the second terminal of the first resistive element, and an output terminal for providing a brown-out detection signal. | 07-28-2011 |
20110267723 | OVERVOLTAGE PROTECTION CIRCUIT FOR AN INTEGRATED CIRCUIT - An overvoltage protection circuit may include a reference voltage generator, a trigger circuit, and a clamping device. The reference voltage generator is for providing a reference voltage that is relatively constant during a powered EOS/ESD event. The trigger circuit is coupled to receive the reference voltage and a power supply voltage. The trigger circuit is for comparing the reference voltage to the power supply voltage. In response to detecting that the power supply voltage is above the reference voltage, the trigger circuit provides a trigger signal having a voltage proportional to a voltage level of the overvoltage event. The clamping device is coupled between a first power supply terminal and a second power supply terminal. The clamping device is for providing a current path between the first and second power supply terminals in response to the trigger signal. | 11-03-2011 |
20120086423 | SWITCHED MODE VOLTAGE REGULATOR AND METHOD OF OPERATION - A voltage regulator includes a transistor, a comparator, and a compensation circuit. The comparator has a first input terminal coupled to receive a clock signal, a second input terminal, and an output terminal coupled to a control electrode of the transistor. The compensation circuit has a first input terminal coupled to receive a reference voltage, a second input terminal coupled to the output terminal of the voltage regulator, and an output terminal coupled to the second input terminal of the comparator. The compensation circuit has a filter circuit. The filter circuit has a first RC time constant during startup of the voltage regulator, and the filter circuit has a second RC time constant during normal operation. Changing the RC time constant for startup prevents an overshoot of an output voltage of the voltage regulator. | 04-12-2012 |
20120105108 | BROWN-OUT DETECTION CIRCUIT - A data processing system ( | 05-03-2012 |
20120281491 | DATA PROCESSING SYSTEM HAVING BROWN-OUT DETECTION CIRCUIT - A data processing system includes a brown-out detection circuit with a first resistive element, a first transistor, a second transistor, and a comparator. The first resistive element has a first terminal coupled to a first power supply voltage terminal, and a second terminal. The first transistor has a first current electrode coupled to the second terminal of the first resistive element, a control electrode, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode coupled to a second power supply voltage terminal. The comparator has a first input terminal coupled to the first terminal of the first resistive element, a second input terminal coupled to the second terminal of the first resistive element, and an output terminal for providing a brown-out detection signal. | 11-08-2012 |
20130113449 | Testing a Switched Mode Supply with Waveform Generator and Capture Channel - A test method and system are provided for testing a switched mode power supply in open loop on an automated test equipment device by applying a low frequency waveform signal ( | 05-09-2013 |
20130234743 | METHOD FOR TESTING COMPARATOR AND DEVICE THEREFOR - An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal. | 09-12-2013 |
20130321071 | SYSTEM AND METHOD FOR CONTROLLING BYPASS OF A VOLTAGE REGULATOR - A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared. | 12-05-2013 |
20140118036 | STSTEM AND METHOD FOR CONTROLLING BYPASS OF A VOLTAGE REGULATOR - A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared. | 05-01-2014 |
20140203794 | METHODS AND STRUCTURES FOR DYNAMICALLY CALIBRATING REFERENCE VOLTAGE - A bandgap reference system has a bandgap circuit, an operational transconductance amplifier, and an offset controller. The bandgap circuit includes a pair of diode devices and has a reference terminal at which is provided a bandgap reference voltage. The bandgap circuit provides a differential output having a first output and a second output. The operational transconductance amplifier has a first input coupled to the first output of the bandgap circuit, a second input coupled to the second output of the bandgap reference circuit, and an output coupled to the reference terminal. The offset controller is coupled to the operational transconductance amplifier and to the first and second outputs of the bandgap circuit. The offset controller trims the operational transconductance amplifier as needed to ensure an offset of the operational transconductance amplifier is below a predetermined level. | 07-24-2014 |
20140266098 | VOLTAGE REGULATOR WITH CURRENT LIMITER - A voltage regulator includes an amplifier having a first input coupled to a first reference voltage and a second input coupled to a voltage feedback signal; a multiplexer having a first input coupled to an output of the amplifier, a second input coupled to a voltage clamp signal, and a control input; and a control circuit having a first input coupled to an over current indicator, a second input coupled to a no over voltage indicator, a third input coupled to a timer signal, and an output coupled to the control input of the multiplexer. | 09-18-2014 |
20140300400 | COMPARATOR AND CLOCK SIGNAL GENERATION CIRCUIT - A comparator used in a clock signal generation circuit has first and second input transistors coupled to input signals of the comparator. First and second hysteresis transistors are coupled between the input transistors and an output stage of the comparator, and apply hysteresis to a comparison of the input signals. First and second hysteresis control transistors are coupled between the input transistors and the hysteresis transistors to isolate the hysteresis transistors from the input transistors under control of a hysteresis enable signal. | 10-09-2014 |
20150247893 | DEVICES AND METHOD FOR TESTING POWER-ON RESET VOLTAGE - A system having a power on reset circuit including a voltage divide), a multiplexer coupled to two outputs of the voltage divider, a first comparator coupled to the multiplexer and a reference, a logic gate coupled to the first comparator, a second comparator coupled to one of the two outputs of the voltage divider, and an emulation gate coupled to the second comparator. | 09-03-2015 |
20150338864 | SUPPLY VOLTAGE REGULATION WITH TEMPERATURE SCALING - A supply voltage regulation system for an IC including a temperature sensor that detects temperature of the IC, a scaling resistor coupled between a power grid and a feedback node of the IC, a regulator amplifier that compares a voltage of the feedback node with a reference voltage for developing a supply voltage for the IC, and a temperature scaling circuit that drives a scaling current to the scaling resistor via the feedback node to adjust the supply voltage based on temperature. The temperature scaling circuit may include one or more comparators that compare a temperature signal with corresponding temperature thresholds for selectively applying one or more bias currents to the scaling resistor. The scaling resistor may be coupled to a hot point of the power grid. A voltage difference between a hot point of a ground grid may be converted to a bias current applied to the scaling resistor. | 11-26-2015 |
20150346748 | SYSTEMS AND METHODS FOR A LOW DROPOUT VOLTAGE REGULATOR - A semiconductor device including a voltage regulator is disclosed. The voltage regulator may include a multipath amplifier stage, a driver stage coupled to the multipath amplifier stage, a dynamic compensation circuit coupled to the multipath amplifier stage, and a current compensation circuit. The dynamic compensation circuit may be operable to provide a varying level of compensation to the multipath amplifier stage, where the varying level of compensation proportional to a current level associated with the load; and the current compensation circuit may be operable to allow a minimum current level at the driver stage. | 12-03-2015 |
20160003908 | METHOD FOR TESTING COMPARATOR AND DEVICE THEREFOR - An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal. | 01-07-2016 |
Patent application number | Description | Published |
20110287948 | MEASUREMENT OF MATERIAL PROPERTIES AND RELATED METHODS AND COMPOSITIONS BASED ON CYTOADHERENCE - The invention in some aspects relates to methods, devices and compositions for evaluating material properties, such as mechanical and rheological properties of substances, particularly biological substances, such as cells, tissues, and biological fluids. In some aspects, the invention relates to methods, devices and compositions for evaluating material properties of deformable objects, such as cells. In further aspects, the invention relates to methods, devices and compositions for diagnosing and/or characterizing disease based on material properties of biological cells. | 11-24-2011 |
20110289043 | COMPUTATIONAL METHODS AND COMPOSITIONS - The invention in some aspects relates to methods, devices and compositions for evaluating material properties, such as mechanical and rheological properties of substances, particularly biological substances, such as cells, tissues, and biological fluids. In some aspects, the invention relates to methods, devices and compositions for evaluating material properties of deformable objects, such as cells. In further aspects, the invention relates to methods, devices and compositions for diagnosing and/or characterizing disease based on material properties of biological cells. | 11-24-2011 |
20120064505 | MEASUREMENT OF MATERIAL PROPERTIES AND RELATED METHODS AND COMPOSITIONS - The invention in some aspects relates to methods, devices and compositions for evaluating material properties, such as mechanical and rheological properties of substances, particularly biological substances, such as cells, tissues, and biological fluids. In some aspects, the invention relates to methods, devices and compositions for evaluating material properties of deformable objects, such as cells. In further aspects, the invention relates to methods, devices and compositions for diagnosing and/or characterizing disease based on material properties of biological cells. | 03-15-2012 |
Patent application number | Description | Published |
20140294841 | T CELL RECEPTOR-LIKE ANTIBODIES SPECIFIC FOR A WTI PEPTIDE PRESENTED BY HLA-A2 - The present invention provides antigen binding proteins that specifically bind to Wilms' tumor protein (WT1), including humanized, chimeric and fully human antibodies against WT1, antibody fragments, chimeric antigen receptors (CARs), fusion proteins, and conjugates thereof. The antigen binding proteins and antibodies bind to HLA-A0201-restricted WT1 peptide. Such antibodies, fragments, fusion proteins and conjugates thereof are useful for the treatment of WT1 associated cancers, including for example, breast cancer, ovarian cancer, prostate cancer, chronic myelocytic leukemia, multiple myeloma, acute lymphoblastic leukemia (ALL), acute myeloid/myelogenous leukemia (AML) and myelodysplastic syndrome (MDS). In more particular embodiments, the anti-WT1/A antibodies may comprise one or more framework region amino acid substitutions designed to improve protein stability, antibody binding and/or expression levels. | 10-02-2014 |
20150259436 | T CELL RECEPTOR-LIKE ANTIBODIES SPECIFIC FOR A WTI PEPTIDE PRESENTED BY HLA-A2 - The present invention provides antigen binding proteins that specifically bind to Wilms' tumor protein (WT1), including humanized, chimeric and fully human antibodies against WT1, antibody fragments, chimeric antigen receptors (CARs), fusion proteins, and conjugates thereof. The antigen binding proteins and antibodies bind to HLA-A0201-restricted WT1 peptide. Such antibodies, fragments, fusion proteins and conjugates thereof are useful for the treatment of WT1 associated cancers, including for example, breast cancer, ovarian cancer, prostate cancer, chronic myelocytic leukemia, multiple myeloma, acute lymphoblastic leukemia (ALL), acute myeloid/myelogenous leukemia (AML) and myelodysplastic syndrome (MDS). In more particular embodiments, the anti-WT1/A antibodies may comprise one or more framework region amino acid substitutions designed to improve protein stability, antibody binding and/or expression levels. | 09-17-2015 |
Patent application number | Description | Published |
20100027355 | PLANAR DOUBLE GATE TRANSISTOR STORAGE CELL - A semiconductor device suitable for use as a storage cell includes a semiconductor body having a top surface and a bottom surface, a top gate dielectric overlying the semiconductor body top surface, an electrically conductive top gate electrode overlying the top gate dielectric, a bottom gate dielectric underlying the semiconductor body bottom surface, an electrically conductive bottom gate electrode underlying the bottom gate dielectric, and a charge trapping layer. The charge trapping layer includes a plurality of shallow charge traps, adjacent the top or bottom surface of the semiconductor body. The charge trapping layer may be of aluminum oxide, silicon nitride, or silicon nanoclusters. The charge trapping layer may located positioned between the bottom gate dielectric and the bottom surface of the semiconductor body. | 02-04-2010 |
20100130002 | MULTILAYERED THROUGH VIA - A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is deposited over the nucleation layer, the tungsten layer having a thickness less than or equal to a critical film thickness sufficient to provide for film integrity and adhesion stability. A stress relief layer of titanium nitride is formed over the tungsten layer and a subsequent tungsten layer is deposited over the stress relief layer. The subsequent tungsten layer has a thickness less than or equal to the critical film thickness. The method further includes planarizing to expose the interlevel dielectric layer and a top of the TSV and backgrinding a bottom surface of the substrate sufficient to expose a bottom portion of the TSV. | 05-27-2010 |
20110151659 | MULTILAYERED THROUGH A VIA - A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is deposited over the nucleation layer, the tungsten layer having a thickness less than or equal to a critical film thickness sufficient to provide for film integrity and adhesion stability. A stress relief layer of titanium nitride is formed over the tungsten layer and a subsequent tungsten layer is deposited over the stress relief layer. The subsequent tungsten layer has a thickness less than or equal to the critical film thickness. The method further includes planarizing to expose the interlevel dielectric layer and a top of the TSV and backgrinding a bottom surface of the substrate sufficient to expose a bottom portion of the TSV. | 06-23-2011 |
20110215411 | Method for Forming an Independent Bottom Gate Connection For Buried Interconnection Including Bottom Gate of a Planar Double Gate MOSFET - A method is provided for making a semiconductor device, which comprises (a) providing a semiconductor structure comprising a top gate ( | 09-08-2011 |
20110237073 | METHOD FOR FORMING A THROUGH SILICON VIA (TSV) - A method of forming a through silicon via includes forming a via opening in a substrate using a hard mask, wherein a polymer is formed in the via opening. A first wet clean removes a first portion of the polymer and forms a first carbon containing oxide along portions of the sidewalls. A first ash process modifies the first carbon containing oxide and removes a second portion of the polymer. A first wet etch removes the modified first carbon containing oxide and a third portion of the polymer. A second ash process forms a second carbon containing oxide along at least a portion of the sidewalls. A second wet etch process removes the second carbon containing oxide and a fourth portions of the polymer. A third ash process forms a third carbon containing oxide along portions of the sidewalls and removes any remaining portions of the polymer. | 09-29-2011 |
20120037969 | MONOLITHIC MICROWAVE INTEGRATED CIRCUIT - Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates ( | 02-16-2012 |
20120074583 | SEMICONDUCTOR STRUCTURE HAVING A THROUGH SUBSTRATE VIA (TSV) AND METHOD FOR FORMING - A structure having a substrate includes an opening in the substrate having depth from a top surface of the substrate to a bottom surface of the substrate. A conductive material fills the opening. The opening has a length direction and a width direction and a first and second feature. The first feature and the second feature are spaced apart by a first length. The first feature has first width as a maximum width of the first feature, and the second feature has a second width as the maximum width of the second feature. The opening has a minimum width between the first feature and the second feature that is no more than one fifth the first length. The first width and the second width are each at least twice the minimum width. | 03-29-2012 |
20130005109 | METHOD FOR FORMING A TOROIDAL INDUCTOR IN A SEMICONDUCTOR SUBSTRATE - A toroidal inductor formed in a semiconductor substrate. Through-silicon vias are used to connect metal layers formed on top and bottom surfaces of the semiconductor substrate. In one embodiment, the vias are elongated and laid out in two concentric circles, an inner circle enclosed by an outer circle. The vias of the outer concentric circle are longer than the vias of the inner circle so that spaces between vias are the same for both circles. In another embodiment, each elongated via may include a plurality of circular vias formed in a line. Metals layers on the top and bottom of the semiconductor substrate are patterned to form wedge shaped connectors between the inner and outer vias to form the spirals of the toroidal inductor. The wedge shaped connectors with elongated vias allow spacing between spirals to be constant. | 01-03-2013 |
20130099312 | SEMICONDUCTOR STRUCTURE HAVING A THROUGH SUBSTRATE VIA (TSV) AND METHOD FOR FORMING - A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type. | 04-25-2013 |
20150228545 | METHODS OF MAKING A MONOLITHIC MICROWAVE INTEGRATED CIRCUIT - Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face ( | 08-13-2015 |
Patent application number | Description | Published |
20110074355 | BATTERY UNIT BALANCING SYSTEM - A battery unit balancing system comprises a discharging circuit and means for connecting the discharging circuit to a battery unit. The discharging circuit is configured such that it is automatically activated, when a voltage of the battery unit exceeds a predetermined threshold, to draw a constant discharging current from the battery unit until the voltage of the battery unit falls below the predetermined threshold. | 03-31-2011 |
20120249154 | GROUND FAULT DETECTION SYSTEM - The present application describes, among other things, a ground fault detection system. The system includes an optocoupler, a current sink, and a first voltage source connected in series. The first voltage source can connect to a negative terminal of a battery unit. Upon connection between a positive terminal of the battery unit and a first node at a ground zero reference level, current can flow through the optocoupler and the current sink to cause the optocoupler to output a ground fault detection signal. | 10-04-2012 |
20120249334 | BATTERY MANAGEMENT SYSTEM - The present application describes, among other things, a battery management system. The battery management system includes a computing device and first and second battery unit monitoring modules. The computing device includes an output data request port and an input data port. Each battery unit monitoring module is connected in parallel to the input data port of the computing device. In response to a data request from the output data request port of the computing device, the first battery unit monitoring module transmits data of the first battery unit to the input data port of the computing device, and transmits a data request to the second battery unit monitoring module. In response to the data request from the first battery unit monitoring module, the second battery unit monitoring module transmits data of the second battery unit to the input data port of the computing device. | 10-04-2012 |
20130241488 | PORTABLE POWER SUPPLY - In one aspect, the present disclosure describes an apparatus that may include a battery unit including one or more lithium-ion battery cells, and a charging unit configured with a first automatic shut-off, where the automatic shut-off is responsive to detection of an upper threshold voltage level of the battery unit. The apparatus may include an inverter configured with a second automatic shut-off, where the second automatic shut-off is responsive to detection of a lower threshold voltage level of the battery unit, and an input connection functionally connected to the charging unit. The apparatus may be configured to isolate the battery unit from the inverter responsive to detecting both (a) the input connection is disconnected from an input voltage source, and (b) the inverter is shut off. | 09-19-2013 |
20140285022 | UNINTERRUPTED LITHIUM BATTERY POWER SUPPLY SYSTEM - An uninterrupted power supply system incorporates a plurality of lithium batteries as a back-up power supply to an AC power supply. In the event that there is an interruption in the AC power supply, a power output switch is automatically activated by a power control system to draw power from a lithium battery pack. In an embodiment, a battery pack is monitored by a battery management system that is coupled to battery monitoring modules couple to each battery. The battery management system may be configured to monitor the voltage and/or temperature of each battery. In another embodiment, an uninterrupted power supply system comprises a battery unit balancing system that maintains each battery within a battery unit below a threshold voltage value. A charging circuit and discharging circuit are used to maintain the batteries in a ready state of charge when not being used for the output power. | 09-25-2014 |
20150185291 | SWITCHED CAPACITOR BATTERY UNIT MONITORING SYSTEM - A switched capacitor battery monitoring system enables reliable measurement of the battery voltages of a plurality of batteries in a battery unit with a single microprocessor and or analog-to-digital converter. A battery unit having a plurality of batteries may have a switched capacitor battery monitor configured on each battery. Each switched capacitor battery monitor utilizes a capacitor that is charged to substantially the same voltage level as the battery it is attached to. The capacitor is isolated from the battery by a switch and the voltage level of the capacitor is provided to an analog-to-digital convened to measure the voltage level of said battery. This method enables the individual battery voltage to be measured and therefore does not measure the cumulative voltage of two or more batteries connected in series. This method maintains the measured voltage below a voltage threshold of the analog-to-digital converter and microprocessor. | 07-02-2015 |
20150188334 | WIRELESS BATTERY MANAGEMENT SYSTEM - A wireless battery management system includes a computing device and first and second battery unit monitoring modules. The computing device includes an output data request port and an input data port. In response to a data request from the output data request port of the computing device, a first battery unit monitoring module transmits data of the first battery unit to the input data port of the computing device wirelessly and may transmits a data request to the second battery unit monitoring module. In response, the second battery unit monitoring module may transmit data of the second battery unit to the input data port of the computing device wirelessly or transmit data of the second battery to the first module for wireless transmission. In addition, each battery unit monitoring module may communicate wirelessly and independently with the computing device. | 07-02-2015 |
20150191162 | INTEGRATED BATTERY CONTROL SYSTEM - An integrated battery control system incorporates a battery management system and a power control system to reliably and safely provide power to vehicles and other mobile devices. The integrated power control system incorporates safety features to protect the batteries from dropping below a threshold voltage or being overcharged, and from operating the vehicle when it is coupled with an AC power supply. An integrated power control system may be contained in a control enclosure having a computing device, battery power input, an AC power input, a power output switch, a power output, a key-switch interface and a shunt to measure current flow. The power control system regulates electrical power delivery to a drive motor and a pre-charge resistor as a function of the battery state of charge. When a battery unit is below a threshold value, power delivery is disabled to the drive motor and a pre-charge resistor. | 07-09-2015 |