| Patent application number | Description | Published |
|---|
| 20090109726 | NON-LINEAR CONDUCTOR MEMORY - A high-speed, low-power memory device comprises an array of non-linear conductors wherein the storage, address decoding, and output detection are all accomplished with diodes or other non-linear conductors. In various embodiments, the row and column resistors are switchable between a high resistance when connected to a row or column that is non-selected, and a low resistance when connected to the selected row and column. | 04-30-2009 |
| 20090161420 | FIELD-EMITTER-BASED MEMORY ARRAY WITH PHASE-CHANGE STORAGE DEVICES - Embodiments of the present invention include systems and methods for three-terminal field-emitter triode devices, and memory arrays utilizing the same. In other embodiments, the field-emitter devices include a volume-change material, capable of changing a measurable electrical property of the devices, and/or three-dimensional memory arrays of the same. | 06-25-2009 |
| 20090219741 | DIAGONAL CONNECTION STORAGE ARRAY - In one aspect, an electronic memory array includes overlapping, generally parallel sets of conductors, and includes storage elements near each point of overlap. One set of conductors has a non-negligible resistance. An address path for each storage element traverses a portion of one each of the first and second sets of conductors and a selectable resistance element. All storage element address paths have substantially equivalent voltage drops across the corresponding storage elements. | 09-03-2009 |
| 20090257269 | Low-Complexity Electronic Circuits and Methods of Forming the Same - An electronic circuit such as a latch or a sequencer includes a plurality of transistors, all of the transistors being either NMOS transistors or PMOS transistors, and dissipates less than or approximately the same amount of power as an equivalent CMOS circuit. | 10-15-2009 |
| 20090296445 | DIODE DECODER ARRAY WITH NON-SEQUENTIAL LAYOUT AND METHODS OF FORMING THE SAME - In various embodiments, an electronic circuit includes an array of locations each corresponding to an intersection of a row and a column, and a plurality of devices each disposed proximate one of the locations, wherein no more than ten contiguous locations lack a proximate device. | 12-03-2009 |
| 20100085830 | Sequencing Decoder Circuit - A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits includes first and second decoder stages. The first decoder stage selects one or more first rows by decoding a first subset of the address bits, and the second decoder stage selects one or more second rows based on locations, within the sequence, of one or more third rows different from the one or more second rows. | 04-08-2010 |
| 20100096610 | PHASE-CHANGE MATERIAL MEMORY CELL - A memory cell includes a current-steering device, a phase-change material disposed thereover, and a heating element and/or a cooling element. | 04-22-2010 |
| 20100149865 | SCR MATRIX STORAGE DEVICE - One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column of the array and the non-addressed columns or rows of the array, respectively, also becomes very large. While the leakage current through any one non-addressed diode on the selected row or column will have little impact on the operation of the device, the cumulative leakage through multiple thousands of non-addressed diodes can become significant. This aggregate leakage current can become great enough that the output voltage can be shifted such that the threshold for distinguishing between a one state and a zero state of the addressed diode location can become obscured and can result in a misreading of the addressed diode location. The present invention is a means to manage the leakage currents in a diode array storage device. This is accomplished by actively changing the forward voltage of the diodes in the storage array such that a diode connected to the selected row line but that is not connected to the selected column line is in its high impedance state and a diode connected to the selected column line but that is not connected to the selected row line is in its high impedance state; only a diode that is connected to both the selected row line and the selected column line will switch to its low impedance state. The present invention is an enhancement to all types of arrays of diodes or arrays of other nonlinear conducting elements including: storage devices, programmable logic devices, display arrays, sensor arrays, and many others. | 06-17-2010 |
| 20100157646 | METHODS AND APPARATUS FOR DISABLING A MEMORY-ARRAY PORTION - A memory device having a plurality of storage locations disposed along a plurality of generally parallel lines includes, connected to the lines, a decoder circuit for selecting one line, and, connected to each line, a line-disabling circuit for selectively preventing the line from being energized during line selection. | 06-24-2010 |
| 20100163836 | LOW-VOLUME PHASE-CHANGE MATERIAL MEMORY CELL - A memory device includes a memory array comprising a plurality of storage locations disposed above a plurality of generally parallel lines, where each storage location comprises a programmable material disposed on a sidewall of a conductive element. | 07-01-2010 |
| 20100164543 | LOW-COMPLEXITY ELECTRONIC ADDER CIRCUITS AND METHODS OF FORMING THE SAME - In various embodiments, an adder circuit includes a plurality of transistors, all of the transistors being of a single type selected from the group consisting of NMOS transistors and PMOS transistors, and dissipates no more power than an equivalent CMOS circuit. | 07-01-2010 |
| 20100165726 | DISCHARGE PHASE CHANGE MATERIAL MEMORY - An information storage array includes a programmable material at a storage location and a capacitor set. A switching network charges the capacitor set to a first voltage and discharges the capacitor set at a second voltage. The second voltage is greater than the first voltage and it or a waveform derived therefrom is applied to the storage location to thereby change a state of the programmable material. | 07-01-2010 |
| 20100165727 | PHASE CHANGE MATERIAL MEMORY HAVING NO ERASE CYCLE - An information storage array includes a programmable material at one or more storage locations and pulse generation circuitry for generating at least two pulses—in particular, a write pulse that writes a value into the programmable material an erase pulse that erases a value from the programmable material. In general, the erase pulse is greater in duration than the write pulse. Either the write pulse or the erase pulse is selected based at least in part on a state of a data bit to be stored in the programmable material. | 07-01-2010 |
| 20100232200 | VERTICAL SWITCH THREE-DIMENSIONAL MEMORY ARRAY - A memory device includes a substrate, and, disposed thereover, an array of vertical memory switches. In some embodiments, each switch has at least three terminals and a cross-sectional area less than 6F | 09-16-2010 |
| 20110019455 | LOW COST HIGH DENSITY RECTIFIER MATRIX MEMORY - A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers. | 01-27-2011 |
| 20110019468 | NON-LINEAR CONDUCTOR MEMORY - A high-speed, low-power memory device comprises an array of non-linear conductors wherein the storage, address decoding, and output detection are all accomplished with diodes or other non-linear conductors. In various embodiments, the row and column resistors are switchable between a high resistance when connected to a row or column that is non-selected, and a low resistance when connected to the selected row and column. | 01-27-2011 |
