| Patent application number | Description | Published |
|---|
| 20080285697 | SYSTEM FOR PROVIDING OPEN-LOOP QUADRATURE CLOCK GENERATION - A system for providing open-loop quadrature clock generation. The system is implemented by a ring oscillator structure that includes input inverters for receiving an input clock, forward direction loop inverters, backward direction loop inverters, one or more outputs, and cross-coupled latches connected between any two opposite nodes. | 11-20-2008 |
| 20080301337 | Memory Systems For Automated Computing Machinery - Memory systems are disclosed that include a memory controller; an outbound link, the memory controller connected to the outbound link, the outbound link comprising a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer, each memory buffer device in the first memory layer connected to the outbound link to receive memory signals from the memory controller. | 12-04-2008 |
| 20090034144 | On-Chip High Frequency Power Supply Noise Sensor - The on-chip power supply noise sensor detects high frequency overshoots and undershoots of the power supply voltage. By creating two identical current sources and attaching a time constant circuit to only one, the high frequency transient behavior differs while the low frequency behavior is equivalent. By comparing these currents, the magnitude of very high frequency power supply noise cars be sensed and used to either set latches or add to a digital counter. This has the advantage of directly sensing the power supply noise in a matter that does not require calibration. Also, since the sensor requires only one power supply, it can he used anywhere on a chip. Finally, it filters out any lower frequency noise that is not interesting to the circuit designer and can he timed to detect down to whatever frequency is needed. | 02-05-2009 |
| 20090201064 | Phase Interpolator System and Associated Methods - A phase interpolator system is disclosed that may include a clock to provide a clock signal, and a control section in communication with the clock to regulate the strength of the clock signal. The system may also include a generator circuit to produce an alternate clock signal based upon the strength of the clock signal received from the control section. | 08-13-2009 |
| 20090202076 | Communications System via Data Scrambling and Associated Methods - A communications system that may include a transmitter, a receiver, connected over a communications network. A communication link on the communications network may transfer data between the transmitter and the receiver. The system may also include a logic unit to scramble a plurality of portions of the data at the transmitter based upon the communication link and may unscramble the plurality of portions of the data at the receiver. As a result, the logic unit may provide improved performance of the communication link and/or reduced power consumption of the communication link. | 08-13-2009 |
| 20100001758 | CONTROLLING FOR VARIABLE IMPEDANCE AND VOLTAGE IN A MEMORY SYSTEM - A memory interface device, system, method, and design structure for controlling for variable impedance and voltage in a memory system are provided. The memory interface device includes a calibration cell configurable to adjust an output impedance relative to an external reference resistor, and driver circuitry including multiple positive drive circuits and multiple negative drive circuits coupled to a driver output in a memory system. The memory interface device further includes impedance control logic to adjust the output impedance of the calibration cell and selectively enable the positive and negative drive circuits as a function of a drive voltage and a target impedance. | 01-07-2010 |
| 20100005202 | DYNAMIC SEGMENT SPARING AND REPAIR IN A MEMORY SYSTEM - A communication interface device, system, method, and design structure for providing dynamic segment sparing and repair in a memory system. The communication interface device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment. | 01-07-2010 |
| 20100005335 | MICROPROCESSOR INTERFACE WITH DYNAMIC SEGMENT SPARING AND REPAIR - A processing device, system, method, and design structure for providing a microprocessor interface with dynamic segment sparing and repair. The processing device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment. | 01-07-2010 |
| 20100005345 | BIT SHADOWING IN A MEMORY SYSTEM - A communication interface device, system, method, and design structure for bit shadowing in a memory system are provided. The communication interface device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The communication interface device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate. | 01-07-2010 |
| 20100005349 | ENHANCED MICROPROCESSOR INTERCONNECT WITH BIT SHADOWING - A processing device, processing system, method, and design structure for an enhanced microprocessor interconnect with bit shadowing are provided. The processing device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The processing device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate. | 01-07-2010 |
| 20100013454 | CONTROLLABLE VOLTAGE REFERENCE DRIVER FOR A MEMORY SYSTEM - A voltage reference driver includes a voltage divider circuit with a voltage reference output node to output a voltage between a first voltage and a second voltage. The voltage reference driver also includes a first selectable impedance circuit coupled to a node at the first voltage and further coupled to the voltage reference output node, and a second selectable impedance circuit coupled to a node at the second voltage and further coupled to the voltage reference output node. Combinations of the first selectable impedance circuit and the second selectable impedance circuit are selectable such that a constant impedance is maintained at the voltage reference output node within a threshold value. | 01-21-2010 |
| 20100019744 | VARIABLE INPUT VOLTAGE REGULATOR - A variable input voltage regulator includes a first circuit configured to convert a first voltage from a first voltage source to a first current, and a second circuit electrically coupled to the first circuit and configured to mirror the first current to a voltage output node. The variable input voltage regulator further includes a third circuit electrically coupled to the voltage output node of the second circuit and configured to supply additional current to the voltage output node from a second voltage of a second voltage source in response to a control input. | 01-28-2010 |
| 20100122011 | Method and Apparatus for Supporting Multiple High Bandwidth I/O Controllers on a Single Chip - An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage. Each physical interface may be programmatically connected to a selected interface controller, such as a memory controller, a PCI Express controller, or an Ethernet controller, for example. A plurality of such controllers may be connected to a switch within the processor design, with the switch also being connected to each physical interface macro. Thus, the physical interface macros may be programmatically connected to a subset of the plurality of controllers. | 05-13-2010 |
| 20100122107 | Physical Interface Macros (PHYS) Supporting Heterogeneous Electrical Properties - An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage. | 05-13-2010 |
| 20100177830 | CONFIGURABLE PRE-EMPHASIS DRIVER WITH SELECTIVE CONSTANT AND ADJUSTABLE OUTPUT IMPEDANCE MODES - Embodiments of the invention are directed to a single driver that can be used to transmit data with configurable levels of pre-emphasis, and can have either a constant or adjustable driver output impendence, selectively. One embodiment, directed to a driver apparatus, is associated with a digital communication channel for transmitting data signals, wherein at least one of the signals includes a higher frequency component. The apparatus comprises a first sub-driver that has a constant output impedance, and is selectively configurable to implement two or more different levels of pre-emphasis. The apparatus further comprises one or more second sub-drivers. A set of connector elements are provided for connecting the first sub-driver and each of the second sub-drivers in parallel relationship with one another, so that the first sub-driver and each of the second sub-drivers all have inputs that respectively receive a specified driver apparatus input signal, and all have outputs that are connected together to selectively provide a specified driver apparatus output impedance. The apparatus further includes a device that is connected to selectively disable and enable each of the second sub-drivers. | 07-15-2010 |
| 20100220536 | ADVANCED MEMORY DEVICE HAVING REDUCED POWER AND IMPROVED PERFORMANCE - A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock. | 09-02-2010 |
