Patent application number | Description | Published |
20100161886 | Architecture for Address Mapping of Managed Non-Volatile Memory - The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture. | 06-24-2010 |
20100287329 | Partial Page Operations for Non-Volatile Memory Systems - A read command initiates reads of pages or portions of pages of non-volatile memory using a memory address that specifies a row, column and length. A host controller can use the read command with a read operation or status request. In some implementations, the memory address further specifies a die or plane and a block. | 11-11-2010 |
20100287353 | Multipage Preparation Commands for Non-Volatile Memory Systems - Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation. | 11-11-2010 |
20100287446 | Low Latency Read Operation for Managed Non-Volatile Memory - In a memory system, a host controller is coupled to a non-volatile memory (NVM) package (e.g., NAND device). The host controller sends a read command to the NVM package requesting a low latency read operation. Responsive to the read command, a controller in the NVM package retrieves the data and sends the data to an ECC engine for correcting. Following the read command, the host controller sends a read status request command to the controller in the NVM package. Responsive to the read status request, the controller sends a status report to the host controller indicating that some or all of the data is available for transfer to the host controller. Responsive to the report, the host controller transfers the data. An underrun status can be determined to indicate that uncorrected data had been transferred to the host controller. | 11-11-2010 |
20110022781 | CONTROLLER FOR OPTIMIZING THROUGHPUT OF READ OPERATIONS - A controller, techniques, systems, and devices for optimizing throughput of read operations in flash memory are disclosed. Various optimizations of throughput for read operations can be performed using a controller. In some implementations, read operations for a multi-die flash memory device or system can be optimized to perform a read request with a highest priority (e.g., an earliest received read request) as soon as the read request is ready. In some implementations, the controller can enable optimized reading from multiple flash memory dies by monitoring a read/busy state for each die and switching between dies when a higher priority read operation is ready to begin. | 01-27-2011 |
20110022819 | INDEX CACHE TREE - Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the location of the first lookup table in non-volatile memory. An index cache tree in volatile memory holds the physical addresses of the most recently written or accessed logical sectors in a compressed format. | 01-27-2011 |
20110066789 | FILE SYSTEM DERIVED METADATA FOR MANAGEMENT OF NON-VOLATILE MEMORY - A file system programs metadata on a non-volatile memory device. The metadata can include data associating files with ranges of logical block addresses. During a garbage collection process, the data can be used to determine portions of physical blocks of the non-volatile memory device that are associated with files that have been deleted. Using the programmed metadata during garbage collection results in erasure of larger portions of blocks and improved wear leveling. | 03-17-2011 |
20120311000 | Pre-organization of Data - In a method of writing data to a file system on a solid state drive, a file stream is opened for writing to a file in the file system. A life expectancy value predicting a length of time the data to be written will be stored in the file system is attached to the file stream. The data is written to the file stream and stored on the solid state storage device according to the life expectancy value attached to the data. In one embodiment, a unique identifier may be used as the life expectancy value for writing a group of related files predicted to be stored in the file system for substantially the same length of time. The life expectancy value may be predicted based on a file type of the file being written. The life expectancy value may be stored as metadata for the file being written. | 12-06-2012 |
20130073800 | Multipage Preparation Commands For Non-Volatile Memory Systems - Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation. | 03-21-2013 |
20130212318 | ARCHITECTURE FOR ADDRESS MAPPING OF MANAGED NON-VOLATILE MEMORY - The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture. | 08-15-2013 |