| Patent application number | Description | Published |
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| 20100277211 | DIGITAL PHASE-LOCKED LOOP WITH TWO-POINT MODULATION USING AN ACCUMULATOR AND A PHASE-TO-DIGITAL CONVERTER - A digital phase-locked loop (DPLL) supporting two-point modulation is described. In one design, the DPLL includes a phase-to-digital converter and a loop filter operating in a loop, a first processing unit for a lowpass modulation path, and a second processing unit for a highpass modulation path. The first processing unit receives an input modulating signal and provides a first modulating signal to a first point inside the loop after the phase-to-digital converter and prior to the loop filter. The second processing unit receives the input modulating signal and provides a second modulating signal to a second point inside the loop after the loop filter. The first processing unit may include an accumulator that accumulates the input modulating signal to convert frequency to phase. The second processing unit may include a scaling unit that scales the input modulating signal with a variable gain. | 11-04-2010 |
| 20100310031 | MULTI-RATE DIGITAL PHASE LOCKED LOOP - A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a DCO output signal and a reference clock and outputs a first stream of digital values. Quantization noise is reduced by clocking the TDC at a high rate. Downsampling circuitry converts the first stream into a second stream. The second stream is supplied to a phase detecting summer of the DPLL such that a control portion of the DPLL can switch at a lower rate to reduce power consumption. The DPLL is therefore referred to as a multi-rate DPLL. A third stream of digital tuning words output by the control portion is upsampled before being supplied to the DCO so that the DCO can be clocked at the higher rate, thereby reducing digital images. In a receiver application, no upsampling is performed and the DCO is clocked at the lower rate, thereby further reducing power consumption. | 12-09-2010 |
| 20110085589 | POWER SPECTRAL DISTRIBUTION MEASUREMENT TO FACILITATE SYSTEM ACQUISITION - Wireless devices and techniques providing improved system acquisition in an environment of multiple co-existing technologies over a common frequency band are disclosed. In one aspect, at a remote terminal, a power spectral distribution (PSD) of received signals is sequentially measured in contiguous segments of a frequency band of interest. One or more characteristics of the measured PSD is compared to at least one predetermined metric to identify the presence or absence of at least one technology type of the received signals in frequency locations across the band. A system acquisition operation is performed in accordance with the identification, such as a tailored scan of channels at locations where a desired technology is identified. | 04-14-2011 |
| Patent application number | Description | Published |
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| 20080232611 | METHOD AND APPARATUS FOR MITIGATING PHASE NOISE - Techniques for mitigating additional phase noise in local oscillator (LO) signals, which may be due to digital noise coupling, are described. A correction signal having an estimate of additional phase noise in an LO signal is derived. The correction signal is applied to a data signal either after downconversion or before upconversion with the LO signal to mitigate the additional phase noise. To derive the correction signal, an input signal having the additional phase noise may be obtained by downconverting a replica LO signal or based on the replica LO signal without downconversion. The input signal may be digitized and filtered to pass a single tone and suppress remaining tones. A replica signal may be derived based on the filtered signal and frequency translated to obtain a phase noise estimate signal at DC. The complex conjugate of the phase noise estimate signal may be provided as the correction signal. | 09-25-2008 |
| 20090086863 | INTERFERENCE DETECTION AND MITIGATION - Techniques for detecting and mitigating interference are described. A device (e.g., a cellular phone) senses interference levels and digitally reconstructs the expected interference in the received signal. The device may correlate the reconstructed interference with the received signal and determine interference in the received signal based on correlation results. The device may adjust the operation of one or more circuit blocks (e.g., a mixer, an LNA, etc.) in a receiver based on the detected interference in the received signal. Alternatively or additionally, the device may condition the digital interference to obtain conditioned reconstructed interference matching the interference in the received signal and may then subtract the conditioned interference from the received signal. | 04-02-2009 |
| 20090086864 | INTERFERENCE DETECTION AND MITIGATION - Techniques for detecting and mitigating interference are described. A device (e.g., a cellular phone) senses interference levels and digitally reconstructs the expected interference in the received signal. The device may correlate the reconstructed interference with the received signal and determine interference in the received signal based on correlation results. The device may adjust the operation of one or more circuit blocks (e.g., a mixer, an LNA, etc.) in a receiver based on the detected interference in the received signal. Alternatively or additionally, the device may condition the digital interference to obtain conditioned reconstructed interference matching the interference in the received signal and may then subtract the conditioned interference from the received signal. | 04-02-2009 |
| 20100066421 | ADAPTIVE CALIBRATION FOR DIGITAL PHASE-LOCKED LOOPS - Techniques for adaptively calibrating a TDC output signal in a digital phase-locked loop (DPLL). In an exemplary embodiment, a calibration factor multiplied to the TDC output signal is adaptively adjusted to minimize a magnitude function of a phase comparator output signal of the DPLL. In an exemplary embodiment, the calibration factor may be adjusted using an exemplary embodiment of the least-mean squares (LMS) algorithm. Further techniques for simplifying the adaptive algorithm for hardware implementation are described. | 03-18-2010 |
| 20100141313 | DIGITAL PHASE-LOCKED LOOP WITH TWO-POINT MODULATION AND ADAPTIVE DELAY MATCHING - A digital phase-locked loop (DPLL) supporting two-point modulation with adaptive delay matching is described. The DPLL includes highpass and lowpass modulation paths that support wideband and narrowband modulation, respectively, of the frequency and/or phase of an oscillator. The DPLL can adaptively adjust the delay of one modulation path to match the delay of the other modulation path. In one design, the DPLL includes an adaptive delay unit that provides a variable delay for one of the two modulation paths. Within the adaptive delay unit, a delay computation unit determines the variable delay based on a modulating signal applied to the two modulation paths and a phase error signal in the DPLL. An interpolator provides a fractional portion of the variable delay, and a programmable delay unit provides an integer portion of the variable delay. | 06-10-2010 |
| 20100215111 | METHODS AND APPARATUS FOR POWER CONTROL BASED ANTENNA SWITCHING - A method for selecting an antenna is described. The method may include transmitting using a first antenna with a first metric and a radio frequency (RF) chain for a first dwelling period. The method may include switching to transmitting using a second antenna with a second metric for a first testing period. The second antenna may use the same RF chain as the first antenna. The first metric may be compared with the second metric to determine an optimal antenna. The optimal antenna may be selected. | 08-26-2010 |
| 20100296502 | I-Q MISMATCH COMPENSATION - Techniques for compensating for I-Q mismatch in a communications receiver. In an exemplary embodiment, incoming I and Q samples are adjusted by multiplying with certain compensation coefficients to generate mismatch-compensated I and Q samples. The compensation coefficients may themselves be calculated and iteratively refined from the mismatch-compensated I and Q samples. Further techniques for partitioning the adjustment and estimation functions among computational hardware are disclosed. In an exemplary embodiment, estimation may be restricted to only those segments of the incoming I and Q samples that fulfill certain conditions, e.g., segments of the incoming I and Q samples known to be statistically uncorrelated and/or to have equal average energy. | 11-25-2010 |
| 20100315169 | PLL DISTURBANCE CANCELLATION - Techniques for cancelling a disturbance signal from a PLL output signal. In an aspect, a cancellation signal is combined with the signal input to a VCO or DCO in the PLL. In a further aspect, the appropriate cancellation signal is derived by analyzing one or more signals within the PLL. The signals within the PLL may be correlated against one or more disturbance signal templates, such as a sinusoid having a known frequency, to derive one or more correlation coefficients. The coefficients may be applied to weight one or more disturbance synthesis functions to generate the cancellation signal. Further aspects provide for joint analysis, synthesis, and cancellation of signals having unknown frequency from the PLL output. | 12-16-2010 |
| 20110136446 | COMBINED INTELLIGENT RECEIVE DIVERSITY (IRD) AND MOBILE TRANSMIT DIVERSITY (MTD) WITH INDEPENDENT ANTENNA SWITCHING FOR UPLINK AND DOWNLINK - Methods and apparatus are provided for allowing a transmitter (Tx) to perform antenna selection independently of a receiver (Rx) in a transceiver supporting both transmit diversity and receive diversity. Certain aspects may utilize a cross switch, which may be used in a parallel or cross configuration, to provide for the independent antenna selection, such that the Rx may maintain the ability to operate on the same antenna as the Tx, on another antenna, or on both antennas for enhanced receive diversity. Furthermore, certain aspects may employ additional switching in the baseband domain in an effort to avoid, or at least reduce, switching glitches in the Rx caused by changing the cross switch configuration. In this manner, the Rx need not re-converge upon antenna switching. | 06-09-2011 |
