| Patent application number | Description | Published |
|---|
| 20080258213 | Shielded Gate Field Effect Transistor - A FET includes a trench in a semiconductor region. The trench has a lower portion with a shield electrode therein, and an upper portion with a gate electrode therein, where the upper portion is wider than the lower portion. The semiconductor region includes a substrate of a first conductivity type and a first silicon region of a second conductivity type over the substrate. The first silicon region has a first portion extending to a depth intermediate top and bottom surfaces of the gate electrode. The first silicon region has a second portion extending to a depth intermediate top and bottom surfaces of the shield electrode. The semiconductor region further includes a second silicon region of the first conductivity type between the lower trench portion and the second portion of the first silicon region that has a laterally-graded doping concentration decreasing in a direction away from the sidewalls of the lower trench portion. | 10-23-2008 |
| 20090111227 | Method for Forming Trench Gate Field Effect Transistor with Recessed Mesas Using Spacers - A method for forming a field effect transistor with an active area and a termination region surrounding the active area includes forming a well region in a first silicon region, where the well region and the first silicon region are of opposite conductivity type. Gate trenches extending through the well region and terminating within the first silicon region are formed. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. The well region is recessed between adjacent trenches to expose upper sidewalls of each dielectric cap. A blanket source implant is carried out to form a second silicon region in an upper portion of the recessed well region between every two adjacent trenches. A dielectric spacer is formed along each exposed upper sidewall of the dielectric cap, with every two adjacent dielectric spacers located between every two adjacent gate trenches forming an opening over the second silicon region. The second silicon region is recessed through the opening between every two adjacent dielectric spacers so that only portions of the second silicon region directly below the dielectric spacers remain. The remaining portions of the second silicon region form source regions. | 04-30-2009 |
| 20090191678 | Method of Forming a Shielded Gate Field Effect Transistor - A semiconductor region with an epitaxial layer extending over the semiconductor region is provided. A first silicon etch is performed to form an upper trench portion extending into and terminating within the epitaxial layer. A protective material is formed extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion. A second silicon etch is performed to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the semiconductor region, such that the lower trench portion is narrower than the upper trench portion. A two-pass angled implant of dopants of the first conductivity type is carried out to form a silicon region of first conductivity type along sidewalls of the lower trench portion, while the protective material blocks the implant dopants from entering the sidewalls of the upper trench portion and the mesa region adjacent the upper trench portion. | 07-30-2009 |
| 20090200606 | Power Device Edge Termination Having a Resistor with One End Biased to Source Voltage - A field effect transistor (FET) includes a source electrode for receiving an externally-provided source voltage. The FET further includes an active region and a termination region surrounding the active region. A resistive element is coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an avalanche current starts to flow in the termination region, and the resistive element is configured to induce a portion of the avalanche current to flow through the termination region and a remaining portion of the avalanche current to flow through the active region. During operation, one end of the resistive element is biased to the source voltage. | 08-13-2009 |
| 20090230465 | Trench-Gate Field Effect Transistors and Methods of Forming the Same - A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region. | 09-17-2009 |
| 20100038708 | Method and Structure for Forming a Shielded Gate Field Effect Transistor - A method of forming a charge balance MOSFET includes the following steps. A substrate with an overlying epitaxial layer both of a first conductivity type, are provided. A gate trench extending through the epitaxial layer and terminating within the substrate is formed. A shield dielectric lining sidewalls and bottom surface of the gate trench is formed. A shield electrode is formed in the gate trench. A gate dielectric layer is formed along upper sidewalls of the gate trench. A gate electrode is formed in the gate trench such that the gate electrode extends over but is insulated from the shield electrode. A deep dimple extending through the epitaxial layer and terminating within the substrate is formed such that the deep dimple is laterally spaced from the gate trench. The deep dimple is filled with silicon material of the second conductivity type. | 02-18-2010 |
| 20100140696 | Trench-Based Power Semiconductor Devices With Increased Breakdown Voltage Characteristics - Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed. | 06-10-2010 |
| 20100140697 | Trench-Based Power Semiconductor Devices with Increased Breakdown Voltage Characteristics - Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed. | 06-10-2010 |
| 20100258855 | Field Effect Transistor with Self-aligned Source and Heavy Body Regions and Method of Manufacturing Same - A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches include a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench. | 10-14-2010 |
| 20100258862 | TRENCH-GATE FIELD EFFECT TRANSISTOR WITH CHANNEL ENHANCEMENT REGION AND METHODS OF FORMING THE SAME - A field effect transistor includes a body region of a first conductivity type in a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminating within the semiconductor region. A source region of the second conductivity type extends in the body region adjacent the gate trench. The source region and an interface between the body region and the semiconductor region define a channel region therebetween which extends along the gate trench sidewall. A channel enhancement region of the second conductivity type is formed adjacent the gate trench. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region. | 10-14-2010 |
| 20110089488 | Power Device with Improved Edge Termination - A field effect transistor includes an active region and a termination region surrounding the active region. A resistive element is coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an avalanche current starts to flow in the termination region, and the resistive element is configured to induce a portion of the avalanche current to flow through the termination region and a remaining portion of the avalanche current to flow through the active region. | 04-21-2011 |
