| Patent application number | Description | Published |
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| 20080197499 | STRUCTURE FOR METAL CAP APPLICATIONS - An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material. | 08-21-2008 |
| 20080203570 | STRUCTURE INCLUDING VIA HAVING REFRACTORY METAL COLLAR AT COPPER WIRE AND DIELECTRIC LAYER LINER-LESS INTERFACE AND RELATED METHOD - Structures including a refractory metal collar at a copper wire and dielectric layer liner-less interface, and a related method, are disclosed. In one embodiment, a structure includes a copper wire having a liner-less interface with a dielectric layer thereabove; a via extending upwardly from the copper wire through the dielectric layer; and a refractory metal collar extending from a side of the via and partially along the liner-less interface. Refractory metal collar prevents electromigration induced slit voiding by improving the interface around the via, and prevents void nucleation from occurring near the via. Also, the refractory metal collar provides electrical redundancy in the presence of voids around the via and dielectric layer liner-less interface. | 08-28-2008 |
| 20080233366 | STRUCTURE AND METHOD FOR SiCOH INTERFACES WITH INCREASED MECHANICAL STRENGTH - Disclosed is a structure and method for forming a structure including a SiCOH layer having increased mechanical strength. The structure includes a substrate having a layer of dielectric or conductive material, a layer of oxide on the layer of dielectric or conductive material, the oxide layer having essentially no carbon, a graded transition layer on the oxide layer, the graded transition layer having essentially no carbon at the interface with the oxide layer and gradually increasing carbon towards a porous SiCOH layer, and a porous SiCOH (pSiCOH) layer on the graded transition layer, the porous pSiCOH layer having an homogeneous composition throughout the layer. The method includes a process wherein in the graded transition layer, there are no peaks in the carbon concentration and no dips in the oxygen concentration. | 09-25-2008 |
| 20080254630 | DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES - Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect. | 10-16-2008 |
| 20080265377 | AIR GAP WITH SELECTIVE PINCHOFF USING AN ANTI-NUCLEATION LAYER - A method of forming cavities within a semiconductor device is disclosed. The method comprises depositing an anti-nucleating layer on the interior surface of cavities within an ILD layer of the semiconductor device. This anti-nucleating layer prevents subsequently deposited dielectric layers from forming within the cavities. By preventing the formation of these layers, the capacitance is reduced, thereby resulting in improved semiconductor performance. | 10-30-2008 |
| 20080296728 | SEMICONDUCTOR STRUCTURE FOR FUSE AND ANTI-FUSE APPLICATIONS - A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier. | 12-04-2008 |
| 20080314754 | INCREASING AN ELECTRICAL RESISTANCE OF A RESISTOR BY NITRIDIZATION - A method for increasing an electrical resistance of a resistor. A fraction F of an exterior surface of a surface layer of a resistor of a semiconductor structure is exposed to the nitrogen-comprising molecules. An anodization electrical circuit is formed and includes: a DC power supply, an electrolytic solution including nitrogen, and the resistor partially immersed in the electrolytic solution. The DC power supply is activated and generates a voltage output, that causes an electrolytic reaction in the electrolytic solution near the resistor. The electrolytic reaction generates nitrogen ions from the nitrogen in the electrolytic solution. The fraction F is exposed to the nitrogen ions. A portion of the surface layer is nitridized by being reacted with the nitrogen ions at a temperature above ambient room temperature such that an electrical resistance of the resistor is increased. | 12-25-2008 |
| 20080315426 | METAL CAP WITH ULTRA-LOW k DIELECTRIC MATERIAL FOR CIRCUIT INTERCONNECT APPLICATIONS - An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided. | 12-25-2008 |
| 20090011526 | INCREASING AN ELECTRICAL RESISTANCE OF A RESISTOR BY NITRIDIZATION - A method for increasing an electrical resistance of a resistor. A semiconductor structure that includes the resistor is placed in a chamber that includes a gas including nitrogen-containing molecules at an nitrogen concentration. A fraction F of an exterior surface of a surface layer of the resistor is exposed to the nitrogen-comprising molecules. A portion of the surface layer is heated at a heating temperature. A combination of the nitrogen concentration and the heating temperature is sufficient to nitridize the portion of the surface layer by reacting the portion with the nitrogen-containing molecules. Heating the portion of the surface layer includes directing a beam of radiation or particles into the portion of the surface layer heat the portion of the surface layer. The portion of the surface layer is nitridized by being reacted with the nitrogen-containing molecules such that an electrical resistance of the resistor is increased. | 01-08-2009 |
| 20090032959 | ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS - Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a first set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors. | 02-05-2009 |
| 20090035954 | INTERCONNECT STRUCTURE WITH GRAIN GROWTH PROMOTION LAYER AND METHOD FOR FORMING THE SAME - In general, the present invention provides an interconnect structure and method for forming the same. This present invention discloses an interconnect structure includes a Cu seeding layer embedded between a diffusion barrier layer and a grain growth promotion layer. Specifically, under the present invention, a diffusion barrier layer is formed on a patterned inter-level dielectric layer. A (Cu) seeding layer is then formed on the diffusion barrier layer, and a grain growth promotion layer is formed on the seeding layer. Once the grain growth promotion layer is formed, post-processing steps (e.g., electroplating and chemical-mechanical polishing) are performed. | 02-05-2009 |
| 20090075472 | METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS - Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure. | 03-19-2009 |
| 20090127711 | INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME - A highly reliable copper interconnect structure and method of fabricating the same is provided. The interconnect structure comprises a metal layer buried between an adjacent upper copper layer and an adjacent lower copper layer structure. More specifically, the interconnect structure comprises a recess formed in a dielectric layer; a barrier metal lining sidewalls of the recess; a first copper layer within the recess; a second copper layer within the recess; and a metal layer buried between the first copper layer and the second copper layer. The method comprises forming a recess in an interlayer dielectric; forming a first copper layer, a metal layer over the first copper layer and a second copper layer over the metal layer, all within the recess. The metal layer is sandwiched between the first copper layer and the second copper layer within the recess. | 05-21-2009 |
| 20090140428 | AIR GAP STRUCTURE HAVING PROTECTIVE METAL SILICIDE PADS ON A METAL FEATURE - A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed. | 06-04-2009 |
| 20090148677 | HIGH ASPECT RATIO ELECTROPLATED METAL FEATURE AND METHOD - Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up. | 06-11-2009 |
| 20090155993 | TERMINAL PAD STRUCTURES AND METHODS OF FABRICATING SAME - Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process. | 06-18-2009 |
| 20090189287 | NOBLE METAL CAP FOR INTERCONNECT STRUCTURES - An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to the formation of the noble metal cap. The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface. | 07-30-2009 |
| 20090194875 | HIGH PURITY Cu STRUCTURE FOR INTERCONNECT APPLICATIONS - A structure and method of forming a high purity copper structure for interconnect applications is described. The structure includes a patterned dielectric material and at least one Cu-containing conductive material having an upper surface embedded within the dielectric material; and a diffusion barrier and a noble metal liner separating the patterned dielectric material from the at least one Cu-containing conductive material; where the Cu-containing conductive material having high purity, C<10 ppm, Cl<10 ppm, S<10 ppm, and uniform impurity. A method of fabricating the interconnect structure is also described. The method includes providing an initial interconnect structure that includes a dielectric having at least one opening; forming a diffusion barrier layer on all exposed surfaces; forming a noble metal layer on the diffusion barrier layer; forming a Cu containing layer on the noble metal layer; and completely filling the at least one opening with the Cu containing layer. | 08-06-2009 |
| 20090200636 | SUB-LITHOGRAPHIC DIMENSIONED AIR GAP FORMATION AND RELATED STRUCTURE - Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer. | 08-13-2009 |
| 20100032829 | STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES - Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire. | 02-11-2010 |
| 20100038783 | METAL CAP FOR BACK END OF LINE (BEOL) INTERCONNECTS, DESIGN STRUCTURE AND METHOD OF MANUFACTURE - A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous. | 02-18-2010 |
| 20100038784 | REDUNDANT BARRIER STRUCTURE FOR INTERCONNECT AND WIRING APPLICATIONS, DESIGN STRUCTURE AND METHOD OF MANUFACTURE - A redundant diffusion barrier structure and method of fabricated is provided for interconnect and wiring applications. The structure can also be a design structure. The structure includes a first liner lining at least one of a trench and a via and a second liner deposited over the first liner. The second liner comprises RuX. X is at least one of Boron and Phosphorous. The structure comprises a metal deposited on the second liner in the at least one trench and via to form a metal interconnect or wiring. | 02-18-2010 |
| 20100047990 | METHOD OF FABRICATING A HIGH Q FACTOR INTEGRATED CIRCUIT INDUCTOR - A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor. | 02-25-2010 |
| 20100051474 | METHOD AND COMPOSITION FOR ELECTRO-CHEMICAL-MECHANICAL POLISHING - Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations. | 03-04-2010 |
| 20100143649 | HIGH ASPECT RATIO ELECTROPLATED METAL FEATURE AND METHOD - Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up. | 06-10-2010 |
| 20100181677 | STRUCTURE WITH SELF ALIGNED RESIST LAYER ON AN INSULATING SURFACE AND METHOD OF MAKING SAME - A structure is provided with a self-aligned resist layer on an insulator surface and non-lithographic method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one of interconnects formed in an insulator material. The method further comprises exposing the resist to energy and developing the resist to expose surfaces of the interconnects. The method further comprises depositing metal cap material on the exposed surfaces of the interconnects. | 07-22-2010 |
| 20100181678 | STRUCTURE WITH SELF ALIGNED RESIST LAYER ON AN INTERCONNECT SURFACE AND METHOD OF MAKING SAME - A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist. | 07-22-2010 |
| 20100283121 | ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS - Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors. | 11-11-2010 |
| 20110003473 | STRUCTURE FOR METAL CAP APPLICATIONS - An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material. | 01-06-2011 |
| 20110092067 | AIR GAP STRUCTURE HAVING PROTECTIVE METAL SILICIDE PADS ON A METAL FEATURE - A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed. | 04-21-2011 |
| 20110101489 | SiCOH DIELECTRIC MATERIAL WITH IMPROVED TOUGHNESS AND IMPROVED Si-C BONDING, SEMICONDUCTOR DEVICE CONTAINING THE SAME, AND METHOD TO MAKE THE SAME - A low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided that includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si—CH | 05-05-2011 |
| 20110111590 | DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES - Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects. | 05-12-2011 |
| 20110163446 | METHOD TO GENERATE AIRGAPS WITH A TEMPLATE FIRST SCHEME AND A SELF ALIGNED BLOCKOUT MASK AND STRUCTURE - A structure and method to produce an airgap on a substrate having a dielectric layer and copper interconnects with sublithographic perforations therein which are ordered throughout the wafer structure in a macro level and a micro level with no change in order orientation and the top layer of the copper interconnects are not exposed. | 07-07-2011 |
