| Patent application number | Description | Published |
|---|
| 20080239779 | System and Method for Detecting Multiple Matches - A system for identifying asserted signals includes a plurality of input ports, a priority encoding module, and a match module. The plurality of input ports receive one of a plurality of input signals. The priority encoding module is coupled to the plurality of input ports and outputs a signal indicating a highest-priority input signal that is asserted. The match module is also coupled to the plurality of input ports and receives a plurality of match detect signals from the priority encoding module. Each match detect signal is associated with a particular input signal and indicates whether another input signal having a higher-priority than the associated input signal is asserted. The match module also generates a multiple match signal based on the input signals and the match detect signals. The multiple match signal indicates whether more than one of the input signals is asserted. | 10-02-2008 |
| 20080272405 | Content addressable memory cell including a junction field effect transistor - A semiconductor device that includes a memory cell having a junction field effect transistor (JFET) used to form a content addressable memory (CAM) cell is disclosed. The JFET may include a data storage region disposed between a first and second insulating region. The data storage region provides a first threshold voltage to the JFET when storing a first data value and provides a second threshold voltage to the JFET when storing a second data value. The memory cell is a dynamic random access memory (DRAM) cell and can be used to form a CAM cell. The CAM cell may be a ternary CAM cell formed with as few as two JFETs. | 11-06-2008 |
| 20080272823 | JFET Passgate Circuit and Method of Operation - A passgate circuit comprises a first depletion mode n-channel JFET, a depletion mode p-channel JFET, and a second depletion mode n-channel JFET. The first depletion mode n-channel JFET has a first terminal coupled to an input port, a second terminal that receives a first control signal, and a third terminal. The depletion mode p-channel JFET has a first terminal coupled to the third terminal of the first depletion mode n-channel JFET, a second terminal that receives a second control signal, and a third terminal. The second depletion mode n-channel JFET has a first terminal coupled to the third terminal of the depletion mode p-channel JFET, a second terminal that receives the first control signal, and a third terminal coupled to an output port. | 11-06-2008 |
| 20080273409 | Junction field effect dynamic random access memory cell and applications therefor - A semiconductor device that includes a memory cell having a junction field effect transistor (JFET) is disclosed. The JFET may include a data storage region disposed between a first and second insulating region. The data storage region provides a first threshold voltage to the JFET when storing a first data value and provides a second threshold voltage to the JFET when storing a second data value. The memory cell is a dynamic random access memory (DRAM) cell. | 11-06-2008 |
| 20080285322 | Junction field effect dynamic random access memory cell and content addressable memory cell - A semiconductor memory device including a dynamic random access memory (DRAM) cell and a ternary content addressable memory (TCAM) cell is disclosed. The DRAM cell may include a data storing portion and a data read portion. The data storing portion and data read portion comprising p-channel junction field effect transistors. The TCAM cell including an x-cell, y-cell, and comparator circuit. The x-cell, y-cell, and comparator circuits comprising p-channel JFETs. | 11-20-2008 |
| 20090033361 | Switching circuits and methods for programmable logic devices - A switching circuit can have a plurality of first signal lines of a programmable logic device, a plurality of second signal lines of the programmable logic device, and a plurality of switch elements. Each switch element can selectively couple one first signal line to a second signal line and include one or more switch junction field effect transistors (JFETs) having a first control gate separated from a second control gate by a channel region. | 02-05-2009 |
| 20090168508 | Static random access memory having cells with junction field effect and bipolar junction transistors - A static random access memory (SRAM) device can include at least one SRAM cell having storage section that includes at least a first junction field effect transistor (JFET) with a gate terminal formed from a semiconductor layer deposited on a substrate surface. The storage section can also include at least a first storage node that provides a potential corresponding to a stored data value. The SRAM cell further includes a first access section that includes at least a first bipolar junction transistor (BJT) having an emitter formed from the semiconductor layer. | 07-02-2009 |
| 20110074498 | Electronic Devices and Systems, and Methods for Making and Using the Same - A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV | 03-31-2011 |
