Patent application number | Description | Published |
20100110755 | FERROELECTRIC RANDOM ACCESS MEMORY DEVICE - A ferroelectric random access memory device has a first bit line, a first ferroelectric capacitor, a second bit line, a second ferroelectric capacitor and a first to fourth MOS transistor. The first bit line is changed to a first data potential according to first data stored in the first ferroelectric capacitor, the second bit line is changed to a second data potential according to second data obtained by inverting a logic of the first data, and then the second MOS transistor and the fourth MOS transistor are turned on. | 05-06-2010 |
20100124092 | FERROELECTRIC MEMORY DEVICE - According to an aspect of the present invention, there is provided a ferroelectric memory device including: a cell unit including: a first select transistor having a first source, a first drain, and a first gate, one of the first source and the first drain being connected to a bit line; and a memory cell unit having a plurality of first memory cells, each of the first memory cells including a first ferroelectric capacitor and a first memory transistor; and a ferroelectric memory fuse including: a second select transistor having a second source, a second drain, and a second gate connected to a second select line, one of the second source and the second drain being connected to one end of the bit line; and a memory fuse unit having a plurality of second memory cells, each of the second memory cells including a second ferroelectric capacitor and a second memory transistor. | 05-20-2010 |
20100157650 | FERROELECTRIC MEMORY - A ferroelectric memory according to an embodiment of the present invention includes a memory cell array including plural memory cells, and provided with plural word lines, plural bit lines, and plural plate lines, each of the plate lines corresponding to at least two of the word lines, an access control circuit configured to perform an access operation to a selected cell which is selected from the memory cells, and a refresh control circuit configured to perform a refresh operation, in a background of the access operation, on a refresh cell which is selected from the memory cells, the refresh control circuit performing the refresh operation when a plate line connected to the selected cell and a bit line connected to the selected cell are at the same potential after the access operation. | 06-24-2010 |
20110058403 | FERRO-ELECTRIC RANDOM ACCESS MEMORY APPARATUS - A ferro-electric random access memory apparatus has a memory cell array in which a plurality of memory cells each formed of a ferro-electric capacitor and a transistor are arranged, word lines are disposed to select a memory cell, plate lines are disposed to apply a voltage to a first end of the ferro-electric capacitor in a memory cell, and bit lines are disposed to read cell data from a second end of the ferro-electric capacitor in the memory cell. The ferro-electric random access memory apparatus has a sense amplifier which senses and amplifies a signal read from the ferro-electric capacitor onto the bit line. The ferro-electric random access memory apparatus has a bit line potential control circuit which exercises control to pull down a voltage on an adjacent bit line adjacent to the selected bit line onto which the signal is read, before operation of the sense amplifier at time of data readout. | 03-10-2011 |
20110063886 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD OF THE SAME - A memory includes a cell region; a spare region including a spare block; a fuse region storing remedy information necessary for an access to the spare block instead of a remedy target block, the fuse region comprising non-defective cells in the remedy target block, or including cells in a first block of the spare region; an initial reading fuse storing a block address for identifying the remedy target block or the first block allocated as the fuse region, and a selection address for selecting a region in the remedy target block or a region in the first block allocated as the fuse region; and a controller configured to acquire the remedy information from the fuse region based on the block address and the selection address, and to change the access to the remedy target block to the access to the spare block based on the remedy information. | 03-17-2011 |
20120246388 | MEMORY SYSTEM, NONVOLATILE STORAGE DEVICE, CONTROL METHOD, AND MEDIUM - According to one embodiment, a memory system includes a nonvolatile storage device and an information processing apparatus. The information processing apparatus includes a first control circuit configured to send a delete notification to the nonvolatile storage device to invalidate data in a first logical address area when read data corresponding to the first logical address area is the same as data expressed by a first function. The nonvolatile storage device include a nonvolatile storage medium, a management table configured to associate a logical address corresponding to valid data for the nonvolatile storage device with a physical address, and a second control circuit configured to update the management table to invalidate a logical address designated by the delete notification, and to send the data expressed by the first function to the information processing apparatus when a logical address included in a read instruction received from the information processing apparatus is invalid. | 09-27-2012 |
20130159785 | SEMICONDUCTOR STORAGE DEVICE, METHOD FOR CONTROLLING THE SAME AND CONTROL PROGRAM - According to one embodiment, a semiconductor memory stores a program for causing a memory controller to operate in at least one of first and second modes. In the first mode, for each of the blocks, the memory controller autonomously erases and writes data and reads the written data, and determines that the block or the semiconductor storage device is defective when a count of errors in the read data exceeds a correction capability or a threshold. In the second mode, when error correction of read substantial data fails, the memory controller reads the substantial data which failed in the error correction using a read level shifted from the present read level. | 06-20-2013 |
20130159814 | SEMICONDUCTOR STORAGE DEVICE, NONVOLATILE SEMICONDUCTOR MEMORY TEST METHOD, AND MEDIUM - According to one embodiment, a semiconductor storage device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a firmware area capable of storing firmware used to execute either a normal mode or an autorun test mode and a user area capable of storing user data. The controller reads the firmware from the nonvolatile semiconductor memory and determines whether the firmware has been set in either the normal mode or the autorun test mode. The controller repeats erasing, writing, and reading in each block in the user area using a cell applied voltage higher than a voltage used in a normal mode, and enters a block where an error has occurred as a bad block. | 06-20-2013 |
20130332802 | SEMICONDUCTOR STORAGE DEVICE, NONVOLATILE SEMICONDUCTOR MEMORY TEST METHOD, AND MEDIUM - According to one embodiment, a semiconductor storage device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a firmware area capable of storing firmware used to execute either a normal mode or an autorun test mode and a user area capable of storing user data. The controller reads the firmware from the nonvolatile semiconductor memory and determines whether the firmware has been set in either the normal mode or the autorun test mode. The controller repeats erasing, writing, and reading in each block in the user area using a cell applied voltage higher than a voltage used in a normal mode, and enters a block where an error has occurred as a bad block. | 12-12-2013 |
20140173268 | INFORMATION PROCESSING APPARATUS, METHOD FOR CONTROLLING INFORMATION PROCESSING APPARATUS, NON-TRANSITORY RECORDING MEDIUM STORING CONTROL TOOL, HOST DEVICE, NON-TRANSITORY RECORDING MEDIUM STORING PERFORMANCE EVALUATION TOOL, AND PERFORMANCE EVALUATION METHOD FOR EXTERNAL MEMORY DEVICE - According to the embodiments, a nonvolatile memory device is configured to store a normal operating system, and store a bootloader. A host device is capable of initiating the normal operating system by using the bootloader. The host device is configured to determine whether a first condition is established based on information obtained from the nonvolatile memory device; and rewrite, when determined the first condition is established, the bootloader so that an emergency software is initiated when booting the host device. The emergency software is executed on the host device. The host device is capable of issuing only a read command to the nonvolatile memory device under a control of the emergency software. | 06-19-2014 |