| Patent application number | Description | Published |
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| 20090059471 | Multilayer Ceramic Capacitor and Production Method of the Same - The invention provides a multilayer ceramic capacitor comprising a capacitor body composed by alternately layering dielectric layers and inner electrode layers, and each of the above mentioned dielectric layers contains a plurality of crystal particles, and grain boundary phases comprising interfacial grain boundaries and triple point grain boundaries formed among a plurality of the crystal particles adjacent to one another, and Si—Ba—O compound being formed in 5% or more of the triple point grain boundaries in the entire triple point grain boundaries per unit surface area of the dielectric layer. Accordingly, the multilayer ceramic capacitor has high relative permittivity and is high the temperature property and highly accelerated life test property. | 03-05-2009 |
| 20090219666 | Dielectric Ceramic, Manufacturing Method Thereof, And Multilayer Ceramic Capacitor - A dielectric ceramic whose primary crystal grains | 09-03-2009 |
| 20100188797 | LAMINATED CERAMIC CAPACITOR - A crystal constituting a dielectric porcelain, comprised of a first crystal group composed of crystal grains of 0.2 atomic % or less calcium concentration and a second crystal group composed of crystal grains of 0.4 atomic % or more calcium concentration, wherein the ratio of concentration of each of magnesium and a first rare earth element contained in a center portion to that contained in a surface layer portion of crystal grains constituting the first crystal group is greater than the corresponding concentration ratio of crystal grains constituting the second crystal group, and wherein on a polished surface resulting from polishing of the surface of the dielectric porcelain, when the area of crystal grains of the first crystal group is referred to as a and the area of crystal grains of the second crystal group referred to as b, the ratio of b/(a+b) is in the range of 0.5 to 0.8. | 07-29-2010 |
| Patent application number | Description | Published |
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| 20090113373 | Layout design apparatus, layout design method, and computer product - A layout design apparatus that limits the maximum wiring density and the maximum edge length of partial regions when determining wiring layout. After determining the wiring layout, the layout design apparatus inserts a dummy into a partial region having a low wiring density and thereby, the minimum wiring density and the minimum edge length of the partial regions are limited. Thus, the respective wiring densities and respective edge lengths of the partial regions are constrained within a constant range and irregularities in the substrate surface after polishing can be suppressed. | 04-30-2009 |
| 20090246893 | SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURING PROCESS EVALUATION METHOD - A method for evaluating a process of manufacturing a semiconductor integrated circuit including a deposition step and a polishing step after the deposition step, the method includes: dividing the semiconductor integrated circuit into a plurality of areas; determining a deposition height after the deposition step for each of the areas; and determining a risk value for each of the areas on the basis of a difference in the deposition height between each of the areas and its adjacent areas. | 10-01-2009 |
| 20100042392 | PLATED FILM THICKNESS CALCULATING METHOD AND PLATED FILM THICKNESS CALCULATING DEVICE - A computer readable recording medium stores therein a plated film thickness calculating program for a semiconductor integrated circuit producing process in which a plating treatment, a polishing treatment and an over-polishing treatment are performed. The plated film thickness calculating program performing a process includes simulating the plating treatment of plating the surface of the substrate for a given thickness of the conductor; calculating a thickness of the conductor to be removed by the polishing treatment until at least a part of the plateaus appears; calculating a maximum thickness of the conductor to be remained on any part of the plateaus after performing the polishing treatment; and repeating the simulating, the thickness calculation and the maximum thickness calculation by changing the given thickness until a minimum of the given thickness is determined in which the maximum thickness of the remaining conductor becomes less than a predetermined level. | 02-18-2010 |
| 20100152875 | ESTIMATION APPARATUS AND ESTIMATION METHOD - An estimation apparatus for estimating a formation of a plurality of wiring layers for an integrated circuit to be manufactured by laminating the wiring layers each formed through a deposition process of a wiring material on a substrate and subsequently polishing the deposited wiring material, the apparatus includes a deposition estimator, a polishing estimator, and an adjuster. The apparatus includes an optimizer configured to optimize distribution of the height of the wiring material for each of the wiring layers within an acceptable range by controlling the adjuster to generate various combinations of adjusted patterns of the wiring layers and by controlling the deposition estimator and the polishing estimator to perform estimation of distribution of deposition height of the wiring material and distribution of the wiring material to be remained after polishing for each of the wiring layers, respectively, for each of the combinations of the adjusted patterns. | 06-17-2010 |
| Patent application number | Description | Published |
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| 20090207556 | DIELECTRIC CERAMIC AND CAPACITOR - The invention relates to a ceramic dielectric material and to capacitors including the ceramic dielectric material. The ceramic dielectric material of the invention exhibits a high relative dielectric constant and a stable temperature characteristic of the relative dielectric constant. | 08-20-2009 |
| 20100067171 | MULTILAYERED CERAMIC CAPACITOR - [Problems] To provide a multilayered ceramic capacitor which in a high-temperature loading test, can be inhibited from decreasing in insulation resistance with time and which can have high insulating properties even when produced without via a reoxidation step. | 03-18-2010 |
| 20100142120 | DIELECTRIC CERAMIC AND CAPACITOR - A dielectric ceramic includes crystal grains containing barium titanate as a main component, magnesium, a rare-earth element, and manganese, wherein the crystal grains have a cubic crystal structure; and the dielectric ceramic contains, per mole of barium, 0.033 to 0.085 mol of magnesium in terms of MgO, 0.1 to 0.2 mol of the rare-earth element (RE) in terms of RE | 06-10-2010 |
