| Patent application number | Description | Published |
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| 20090050951 | Semiconductor Device and Method of Manufacturing the Same - A method of manufacturing a semiconductor device according to an embodiment of the present invention includes depositing first to third mask layers above a substrate, processing the third mask layer, processing the second mask layer, slimming the second mask layer in an L/S section and out of the L/S section, peeling the third mask layer in the L/S section and out of the L/S section, forming spacers on sidewalls of the second mask layer in the L/S section and out of the L/S section, etching the second mask layer in the L/S section, under a condition that the second mask layer out of the L/S section Is covered with a resist, to remove the second mask layer in the L/S section while the second mask layer out of the L/S section remains, and processing the first mask layer by etching, using the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section as a mask, the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section being thinned by the etching. | 02-26-2009 |
| 20090096007 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture. | 04-16-2009 |
| 20110097888 | Semiconductor memory device and method of manufacturing the same - A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture. | 04-28-2011 |
| Patent application number | Description | Published |
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| 20100056794 | PROCESS FOR THE PREPARATION OF 2,5-BIS-(2,2,2-TRIFLUOROETHOXY)-N-(2-PIPERIDYL-METHYL)-BENZAMIDE AND SALTS THEREOF - Process for the preparation of 2,5-bis(2,2,2-trifluoroethoxy)-N-(2-piperidylmethyl)benzamide, its pharmaceutically acceptable salts and important intermediates thereof that involves 1,4-dihalotoluenes as starting material. The method involves a technique for preparing the starting material 2,5-bis(2,2,2-trifluoroethoxy)toluene in high yields by reacting 1,4-dibromotoluene with 2,2,2-trifluoroethanol in presence of a base and a copper-containing catalyst. | 03-04-2010 |
| 20100063292 | PROCESS FOR THE PREPARATION OF TRIFLUOROETHOXYTOLUENES. - The present invention relates to an process for the preparation 2,5-bis(2,2,2-trifluoroethoxy)toluene [II]. The compound 2,5-bis(2,2,2-trifluoroethoxy)toluene is useful as intermediate for pharmaceutical industry, especially useful as an intermediate for the preparation of Flecainide and pharmaceutically acceptable salts. | 03-11-2010 |
