Patent application number | Description | Published |
20090066852 | Methods for Reducing Channel Change Times in a Digital Video Apparatus - A digital video apparatus provides reduced channel change times. According to an exemplary embodiment, the digital video apparatus includes at least one receiver for receiving first and second video streams representing the same program, wherein the first video stream has at least one characteristic different from the second video stream; a first signal processor for processing the first video stream to generate a first processed video stream; a second signal processor for processing the second video stream to generate a second processed video stream having a delay with respect to the first processed video stream; a renderer for rendering the second processed video stream responsive to a channel change command; and a switch for switching from the second processed video stream to the first processed video stream after the renderer begins rendering the second processed video stream, and thereby causing the renderer to begin rendering the first processed video stream. | 03-12-2009 |
20090245393 | Method and Apparatus For Fast Channel Change For Digital Video - There are provided methods and apparatus for fast channel change for digital video. An apparatus includes at least one encoder for receiving normal video data and channel change video data and encoding the normal video data and the channel change video data in a normal video stream and a channel change video stream, respectively, using a common system clock to provide synchronization between the normal video stream and the channel change video stream. The normal video stream and the channel change video stream are encoded for transport separately at a transport level. | 10-01-2009 |
20100046634 | Video data loss recovery using low bit rate stream in an iptv system - A system and method for recovering from data loss are described including monitoring a first bit rate video data bit stream to determine if there is frame loss or damage, multiplexing decoding parameters of a second bit rate video data bit stream, the second bit rate video data bit stream and the first bit rate video data bit stream, if there is frame loss or damage, demultiplexing the first bit rate video data bit stream and the second bit rate video data bit stream, decoding the first bit rate video data bit stream, removing damaged frames from the first bit rate video data bit stream, decoding the second bit rate video data bit stream, up-sampling frames from said processed second bit rate video data bit stream if said processed second bit rate video data bit stream has a lower resolution than said processed first bit rate video data bit stream and merging frames from the second bit rate video data bit stream and the first bit rate video data bit stream. | 02-25-2010 |
20100064316 | METHOD FOR REDUCING CHANNEL CHANGE TIMES AND SYNCHRONIZING AUDIO/VIDEO CONTENT DURING CHANNEL CHANGE - A digital A/V apparatus provides reduced channel changes times and maintains synchronization between audio and video content during a channel change event. According to an exemplary embodiment, the digital A/V apparatus includes at least one signal receiver for receiving a first audio stream, a first video stream and a second video stream, wherein the first and second video streams represent the same program and the first video stream has at least one characteristic different from the second video stream; a first audio signal processor for processing the first audio stream to generate a first processed audio stream; a first video signal processor for processing the first video stream to generate a first processed video stream; a second video signal processor for processing the second video stream to generate a second processed video stream having a delay with respect to the first processed video stream; a first buffer for buffering the first processed audio stream to provide de-jittering; a renderer for rendering the first processed audio stream and the second processed video stream in response to a channel change command; a switch for switching from the second processed video stream to the first processed video stream after the renderer begins rendering the second processed video stream, and thereby causing the renderer to begin rendering the first processed video stream; and whereby synchronization between the first processed audio stream and the first processed video stream is maintained during a channel change event. | 03-11-2010 |
Patent application number | Description | Published |
20120280370 | SEMICONDUCTOR DEVICE DEVOID OF AN INTERFACIAL LAYER AND METHODS OF MANUFACTURE - A method of forming a dielectric stack devoid of an interfacial layer includes subjecting an exposed interfacial layer provided on a semiconductor material to a low pressure thermal anneal process for a predetermined time period at a temperature of about 900° C. to about 1000° C. with an inert gas purge. A semiconductor structure is also disclosed, with a dielectric stack devoid of an interfacial layer. | 11-08-2012 |
20120329230 | FABRICATION OF SILICON OXIDE AND OXYNITRIDE HAVING SUB-NANOMETER THICKNESS - A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000° C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000° C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0.5 Å to 10 Å. | 12-27-2012 |
20130049142 | TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE - Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO | 02-28-2013 |
20130082332 | METHOD FOR FORMING N-TYPE AND P-TYPE METAL-OXIDE-SEMICONDUCTOR GATES SEPARATELY - Semiconductor devices with replacement gate electrodes are formed with different materials in the work function layers. Embodiments include forming first and second removable gates on a substrate, forming first and second pairs of spacers on opposite sides of the first and second removable gates, respectively, forming a hardmask layer over the second removable gate, removing the first removable gate, forming a first cavity between the first pair of spacers, forming a first work function material in the first cavity, removing the hardmask layer and the second removable gate, forming a second cavity between the second pair of spacers, and forming a second work function material, different from the first work function material, in the second cavity. | 04-04-2013 |
20130126986 | GERMANIUM OXIDE FREE ATOMIC LAYER DEPOSITION OF SILICON OXIDE AND HIGH-K GATE DIELECTRIC ON GERMANIUM CONTAINING CHANNEL FOR CMOS DEVICES - A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region. | 05-23-2013 |
20130181260 | METHOD FOR FORMING N-SHAPED BOTTOM STRESS LINER - Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner. | 07-18-2013 |
20130277765 | SEMICONDUCTOR DEVICE INCLUDING GRADED GATE STACK, RELATED METHOD AND DESIGN STRUCTURE - A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region. | 10-24-2013 |
20130330843 | METHOD OF MANUFACTURING SCALED EQUIVALENT OXIDE THICKNESS GATE STACKS IN SEMICONDUCTOR DEVICES AND RELATED DESIGN STRUCTURE - A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH | 12-12-2013 |
20140001570 | COMPOSITE HIGH-K GATE DIELECTRIC STACK FOR REDUCING GATE LEAKAGE | 01-02-2014 |
20140042546 | STRUCTURE AND METHOD TO FORM INPUT/OUTPUT DEVICES - A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters. | 02-13-2014 |
20140061819 | GERMANIUM OXIDE FREE ATOMIC LAYER DEPOSITION OF SILICON OXIDE AND HIGH-K GATE DIELECTRIC ON GERMANIUM CONTAINING CHANNEL FOR CMOS DEVICES - A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region. | 03-06-2014 |
20140070334 | SEMICONDUCTOR DEVICE INCLUDING GRADED GATE STACK, RELATED METHOD AND DESIGN STRUCTURE - A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region. | 03-13-2014 |
20140120708 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING REPLACEMENT METAL GATE PROCESS INCORPORATING A CONDUCTIVE DUMMY GATE LAYER - A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate. | 05-01-2014 |
20140183051 | DEPOSITION OF PURE METALS IN 3D STRUCTURES - A system and method generate atomic hydrogen (H) for deposition of a pure metal in a three-dimensional (3D) structure. The method includes forming a monolayer of a compound that includes the pure metal. The method also includes depositing the monolayer on the 3D structure and immersing the 3D structure with the monolayer in an electrochemical cell chamber including an electrolyte. Applying a negative bias voltage to the 3D structure with the monolayer and a positive bias voltage to a counter electrode generates atomic hydrogen from the electrolyte and deposits the pure metal from the monolayer in the 3D structure. | 07-03-2014 |
20140187028 | Concurrently Forming nFET and pFET Gate Dielectric Layers - Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region. | 07-03-2014 |
20140264015 | DYNAMIC PEAK TRACKING IN X-RAY PHOTOELECTRON SPECTROSCOPY MEASUREMENT TOOL - Systems and methods for performing X-ray Photoelectron Spectroscopy (XPS) measurements in a semiconductor environment are disclosed. A reference element peak is selected and tracked as part of the measurement process. Peak shift of the reference element peak, in electron volts (eV) is tracked and applied to other portions of acquired spectrum to compensate for the shift, which results from surface charge fluctuation. | 09-18-2014 |
20140308821 | HYDROXYL GROUP TERMINATION FOR NUCLEATION OF A DIELECTRIC METALLIC OXIDE - A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations. | 10-16-2014 |
20160005831 | FIELD EFFECT TRANSISTORS HAVING MULTIPLE EFFECTIVE WORK FUNCTIONS - Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions. | 01-07-2016 |
20160027640 | HYDROXYL GROUP TERMINATION FOR NUCLEATION OF A DIELECTRIC METALLIC OXIDE - A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations. | 01-28-2016 |
Patent application number | Description | Published |
20130017577 | METHODS FOR ENHANCED PROTEIN PRODUCTION - The present invention provides a method of increasing protein production in a cell culture by growing cells that produce the protein (e.g., the growth phase) in a perfusion cell culture to a high cell density (i.e., at least above about 40×10 | 01-17-2013 |
20130252327 | Methods Of Gene Amplification And Expression - Disclosed are methods relating to amplification and expression of a nucleic acid sequence encoding a polypeptide of interest in recombinant cells, and cell lines and polypeptides produced from such methods. The methods disclosed herein permit the amplification of cell lines that express a polypeptide of interest in a relatively short period of time through the use of a bioreactor. | 09-26-2013 |
20140106405 | MAMMALIAN CELL CULTURE PROCESSES FOR PROTEIN PRODUCTION - The present invention describes methods and processes for the production of proteins by animal cell or mammalian cell culture. In one aspect, the methods comprise the growth of cells in a growth factor/protein/peptide free medium. In another aspect, the methods comprise the addition of growth factors during the production phase. The methods sustain a high viability of the cultured cells, and can yield an increased end titer of protein product, and a high quality of protein product. | 04-17-2014 |
20140302581 | METHODS FOR ENHANCED PROTEIN PRODUCTION - The present invention provides a method of increasing protein production in a cell culture by growing cells that produce the protein (e.g., the growth phase) in a perfusion cell culture to a high cell density (i.e., at least above about 40×10 | 10-09-2014 |
Patent application number | Description | Published |
20110178007 | SPIRO-IMIDAZOLONE DERIVATIVES AS GLUCAGON RECEPTOR ANTAGONISTS - The present invention relates to compounds of the general formula: (I) wherein ring A, ring B, R | 07-21-2011 |
20130012434 | NOVEL SPIRO IMIDAZOLONES AS GLUCAGON RECEPTOR ANTAGONISTS, COMPOSITIONS, AND METHODS FOR THEIR USE - The present invention relates to compounds of the general formula: wherein ring A, ring B, R1, R3, Z, L1, and L2 are selected independently of each other and are as defined herein, to compositions comprising the compounds, and to methods of using the compounds as glucagon receptor antagonists and for the treatment or prevention of type 2 diabetes and conditions related thereto. | 01-10-2013 |
20130012493 | NOVEL SPIRO IMIDAZOLONE DERIVATIVES AS GLUCAGON RECEPTOR ANTAGONISTS, COMPOSITIONS, AND METHODS FOR THEIR USE - The present invention relates to compounds of the general formula (I): wherein ring A, ring B, G, R | 01-10-2013 |
20130123315 | SUBSTITUTED IMIDAZOLONES, COMPOSITIONS CONTAINING SUCH COMPOUNDS AND METHODS OF USE - The present invention relates to compounds of the general structure shown in Formula (A): (A): and includes pharmaceutically acceptable salts, solvates, esters, prodrugs, tautomers, and isomers of said compounds. Pharmaceutical compositions and methods of treatment are also included. | 05-16-2013 |
20140128368 | SUBSTITUTED CYCLOPROPYL COMPOUNDS, COMPOSITIONS CONTAINING SUCH COMPOUNDS, AND METHODS OF TREATMENT - Substituted cyclopropyl compounds of the formula I: and pharmaceutically acceptable salts thereof are disclosed as useful for treating or preventing type 2 diabetes and similar conditions. The compounds are useful as agonists of the G-protein coupled receptor GPR-119. Pharmaceutical compositions and methods of treatment are also included. | 05-08-2014 |
20140199263 | HETEROCYCLIC-SUBSTITUTED BENZOFURAN DERIVATIVES AND METHODS OF USE THEREOF FOR THE TREATMENT OF VIRAL DISEASES - The present invention relates to compounds of formula (I) that are useful as hepatitis C virus (HCV) NS5B polymerase inhibitors, the synthesis of such compounds, and the use of such compounds for inhibiting HCV NS5B polymerase activity, for treating or preventing HCV infections and for inhibiting HCV viral replication and/or viral production in a cell-based system. | 07-17-2014 |
20140213571 | TETRACYCLIC HETEROCYCLE COMPOUNDS AND METHODS OF USE THEREOF FOR THE TREATMENT OF VIRAL DISEASES - The present invention relates to compounds of formula (I) that are useful as hepatitis C virus (HCV) NS5B polymerase inhibitors, the synthesis of such compounds, and the use of such compounds for inhibiting HCV NS5B polymerase activity, for treating or preventing HCV infections and for inhibiting HCV viral replication and/or viral production in a cell-based system. | 07-31-2014 |
20150246902 | SUBSTITUED BENZOFURAN COMPOUNDS AND METHODS OF USE THEREOF FOR THE TREATMENT OF VIRAL DISEASES - The present invention relates to compounds of formula (I) that are useful as hepatitis C virus (HCV) NS5B polymerase inhibitors, the synthesis of such compounds, and the use of such compounds for inhibiting HCV NS5B polymerase activity, for treating or preventing HCV infections and for inhibiting HCV viral replication and/or viral production in a cell-based system. | 09-03-2015 |
20150361101 | TETRACYCLIC HETEROCYCLE COMPOUNDS AND METHODS OF USE THEREOF FOR THE TREATMENT OF HEPATITIS C - The present invention relates to compounds of formula I that are useful as hepatitis C virus (HCV) NS5B polymerase inhibitors, the synthesis of such compounds, and the use of such compounds for inhibiting HCV NS5B polymerase activity, for treating or preventing HCV infections and for inhibiting HCV viral replication and/or viral production in a cell-based system. | 12-17-2015 |
20150368246 | TETRACYCLIC HETEROCYCLE COMPOUNDS AND METHODS OF USE THEREOF FOR THE TREATMENT OF HEPATITIS C - The present invention relates to compounds of formula I that are useful as hepatitis C virus (HCV) NS5B polymerase inhibitors, the synthesis of such compounds, and the use of such compounds for inhibiting HCV NS5B polymerase activity, for treating or preventing HCV infections and for inhibiting HCV viral replication and/or viral production in a cell-based system. I | 12-24-2015 |
20150368265 | TETRACYCLIC HETEROCYCLE COMPOUNDS AND METHODS OF USE THEREOF FOR THE TREATMENT OF HEPATITIS C - The present invention relates to compounds of formula (I) that are useful as hepatitis C virus (HCV) NS5B polymerase inhibitors, the synthesis of such compounds, and the use of such compounds for inhibiting HCV NS5B polymerase activity, for treating or preventing HCV infections and for inhibiting HCV viral replication and/or viral production in a cell-based system. I | 12-24-2015 |