Patent application number | Description | Published |
20080225591 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory according to an aspect of the invention includes memory cell arrays including plural cell units, a power supply pad disposed on one end in a first direction of the memory cell arrays, and page buffers disposed in the first direction of the memory cell arrays. The nonvolatile semiconductor memory also includes plural bit lines which are disposed on the memory cell arrays while extending in the first direction and a first power supply line which is disposed on the plural bit lines on the memory cell arrays to connect the power supply pad and the page buffers. | 09-18-2008 |
20090161427 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive. | 06-25-2009 |
20090303799 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ERASING METHOD THEREOF - A non-volatile semiconductor memory device including a NAND cell unit with a plurality of electrically rewritable and non-volatile memory cells connected in series, one end thereof being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, wherein the memory device has an erase-verify mode for verifying an erase state of the memory cells in the NAND cell unit, the erase-verify mode including two verify-read operations adapted according to cell ranges to be erase-verified in the NAND cell unit. | 12-10-2009 |
20100067300 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes: a memory cell array configured to have a plurality of blocks arranged thereon, each of the blocks being configured by an assembly of NAND cell units, each of the NAND cell units including a plurality of nonvolatile memory cells connected in series and word lines configured to commonly connect control gates of the memory cells. A data erase operation is executed by first applying a pre-charge voltage to the word lines, then setting to a floating state the word lines in a non-selected block where erasure of data is not to be executed, applying a certain voltage to the word lines in a selected block where erasure of data is to be executed and applying an erase voltage to a well where the memory cell array is formed, thereby altering a threshold voltage of the memory cells in the selected block. | 03-18-2010 |
20100124111 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A nonvolatile semiconductor memory device comprises: a memory cell array including a plurality of memory cell units each including memory cells, a plurality of bit lines, and a common source line; a sense amplifier operative to read data from a selected memory cell; a control circuit operative to control a read operation of the sense amplifier; and a cell source monitoring circuit operative to detect a voltage of the common source line, compare the detected voltage of the common source line with a reference voltage, and output a read control signal. The sense amplifier is configured to read data from the selected memory cell through at least two cycles. The control circuit is configured to perform control to determine whether the data reading is to be ended after a first reading cycle or a second reading cycle is to be carried out, based on the read control signal. | 05-20-2010 |
20100165733 | NAND NONVOLATILE SEMICONDUCTOR MEMORY - A NAND nonvolatile semiconductor memory includes a plurality of series-connected memory cells each includes a charge storage layer and control gate electrode, a plurality of word lines respectively connected to control gate electrodes of the memory cells, a first selection transistor connected between one end of the memory cells and a source line, a second selection transistor connected between the other end of the memory cells and a bit line, and a driver configured to control voltages applied to the word lines. The driver applies a first voltage to a first word line connected to a selected memory cell, and applies a cutoff voltage that cuts off a channel of a memory cell to second word lines of a number not less than three arranged side by side on the source line side with respect to the first word line during a write operation. | 07-01-2010 |
20100195391 | SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS EACH INCLUDING A CHARGE ACCUMULATION LAYER AND A CONTROL GATE - A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M08-05-2010 | |
20140085977 | SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS EACH INCLUDING A CHARGE ACCUMULATION LAYER AND A CONTROL GATE - A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M03-27-2014 | |