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Daga, US
Anand Daga, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120096424 | Interconnect and Transistor Reliability Analysis for Deep Sub-Micron Designs - A system and method for providing a statistical budgeting approach to modeling reliability effects such as interconnect electromigration (EM), transistor time-dependant dielectric breakdown (TDDB), hot-carrier injection effects (HCI) and bias temperature instability (BTI) is disclosed. A static analysis flow captures the effects of design topology, switching constraints, interactions between signal nets and supply rails as well as thermal gradients due to interconnect and transistor self as well as mutual heating, and was used to verify successive iterations of deep sub-micron integrated circuit designs. | 04-19-2012 |
Bharat Daga, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090184735 | AUTOMATIC PHASE-DETECTION CIRCUIT FOR CLOCKS WITH KNOWN RATIOS - An automatic phase detection circuit for generating an internal synchronization signal when two clock input signals achieve a certain phase relationship. No external reference signal is required. The logic state of one clock is sampled on the active edge of the other clock and stored in a shift register. The content of the shift register is compared to a pre-defined signature and a sync signal is generated when the content matches the pre-defined signature. A mask register may be used to define which bits of the shift register and pre-defined signature are compared. | 07-23-2009 |
Bharat K. Daga, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100241814 | BANDWIDTH-EFFICIENT DIRECTORY-BASED COHERENCE PROTOCOL - Some embodiments of the present invention provide a system that processes a request for a cache line in a multiprocessor system that supports a directory-based cache-coherence scheme. During operation, the system receives the request for the cache line from a requesting node at a home node, wherein the home node maintains directory information for all or a subset of the address space which includes the cache line. Next, the system performs an action at the home node, which causes a valid copy of the cache line to be sent to the requesting node. The system then completes processing of the request at the home node without waiting for an acknowledgment indicating that the requesting node received the valid copy of the cache line. | 09-23-2010 |
| 20100332944 | FACILITATING ERROR DETECTION AND CORRECTION AFTER A MEMORY COMPONENT FAILURE - Some embodiments of the present invention provide a system that can be reconfigured to provide error detection and correction after a failure of a memory component in a memory system. During operation, the system accesses a block of data from the memory system, wherein each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including two checkbit columns containing checkbits, and C-2 data-bit columns containing data bits, wherein each column is stored in a different memory component, and wherein the checkbits are generated from the data bits to provide block-level detection and correction for a failed memory component. Next, upon examining the block of data, the system determines that a specific memory component in the memory system has failed. If the failed memory component contains a data-bit column for the block of data, the system uses checkbits from the two checkbit columns to correct the data-bit column, and then stores the corrected data-bit column. Next, the system generates and stores new checkbits in a functioning memory component, wherein the new checkbits provide single-error-correction and double-error-detection for erroneous bits in the block of data, but do not provide for detection and correction of a failed memory component. | 12-30-2010 |
| 20110047346 | EFFICIENT INTERLEAVING BETWEEN A NON-POWER-OF-TWO NUMBER OF ENTITIES - Some embodiments of the present invention provide a system that maps an address to an entity, wherein the mapping interleaves addresses between a number of entities. During operation, the system receives an address A from a set of X consecutive addresses, wherein the address A is to be mapped to an entity E in a set of Y entities, and wherein Y need not be a power of two. Next, the system obtains F=floor(log | 02-24-2011 |
| 20110289368 | MEMORY SYSTEM THAT SUPPORTS PROBALISTIC COMPONENT-FAILURE CORRECTION WITH PARTIAL-COMPONENT SPARING - The disclosed embodiments relate to a memory system that facilitates probabilistic error correction for a failed memory component with partial-component sparing. During operation, the memory system accesses blocks of data, wherein each block of data includes an array of bits logically organized into R rows and C columns. The C columns include (1) a row-checkbit column containing row-parity bits for each of the R rows, (2) an inner-checkbit column containing X=R−S inner checkbits and S spare bits, and ( | 11-24-2011 |
| 20110289381 | MEMORY SYSTEM THAT PROVIDES GUARANTEED COMPONENT-FAILURE CORRECTION WITH DOUBLE-ERROR CORRECTION - The disclosed embodiments relate to a memory system that provides guaranteed component-failure correction and double-error correction. During operation, the memory system accesses a block of data, wherein each block of data in the memory system includes an array of bits logically organized into R rows and C columns. The C columns include (1) a row-checkbit column containing row checkbits for each of the R rows, (2) an inner-checkbit column containing R inner checkbits, and (3) C-2 data-bit columns containing databits. In addition, each column is stored in a different memory component, and the checkbits are generated from the databits to provide block-level correction for a failed memory component, and double-error correction for errors in different memory components. Next, the system calculates a row syndrome and an inner syndrome for the block of data, wherein the inner syndrome that results from any two-bit error in the same row is unique. If the row syndrome and the inner syndrome are both non-zero, the system determines from the row syndrome and the inner syndrome whether errors in the block of data are associated with a failed memory component. If not, and if exactly two bits in the row syndrome are one, the system assumes that there exists a single-bit error in each of the two rows which have a row syndrome of one, and compares the calculated inner syndrome against inner syndromes for all possible combinations of one-bit errors occurring in each of the two rows. Then, if the comparison matches a given inner syndrome, the system corrects the two bits associated with the given inner syndrome. | 11-24-2011 |
Bharat K. Daga, Framont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100077240 | METHODS AND APPARATUSES FOR REDUCING POWER CONSUMPTION OF FULLY-BUFFERED DUAL INLINE MEMORY MODULES - Methods and apparatuses are presented for reducing the power consumed in an in-line memory module. In some embodiments, the method may include monitoring a memory requirement of a computer system, the computer system comprising a plurality of memory modules. In the event that the memory requirement changes, unmapping at least one of the plurality of memory modules and maintaining a low power state for the at least one unmapped memory module. The method may further comprise selectively re-initializing the plurality of memory modules such that the at least one unmapped memory module remains in a low power state while the remainder of the plurality of memory modules are in a non-low power state. Where, in the event that the memory requirement changes again, the method also may comprise re-programming the memory controller with an identifier associated with the at least one unmapped memory module. | 03-25-2010 |
Gaurav Daga, Redmond, WA US
| Patent application number | Description | Published |
|---|---|---|
| 20080201485 | Printer user interface redirection over a terminal services session - User interface (“UI”) redirection for a local device, such as a printer that is operatively coupled to a client, is provided by an arrangement in which a dummy driver is installed on the terminal server. When an application on the terminal server makes a call to show a UI, the dummy driver redirects the call to a process operating on the client that exposes the specific UI associated with the local device. User input to the UI indicative of preferences and/or other user-selected parameters is recorded and passed to the terminal server through the dummy driver and reported to the calling application. In an illustrative example, the terminal server and client communicate over a virtual channel using a remote desktop protocol in order to redirect print jobs to a local printer that is coupled to the client either directly or over a network such as a local area network. | 08-21-2008 |
| 20080246985 | Printer Redirection - In client-server architectures, systems and methods for XPS based printer redirection are disclosed. In an implementation, a client computing device issues a print command to print an application hosted on a server computing device. The server computing device implements a generic printer driver to emulate exact properties of a client printer driver installed in the client computing device. The generic printer driver redirects one or more calls related to printer settings to the client printer driver. The client computing device returns the printer settings which are combined with the application (to be printed) to generate an XPS file. The XPS file is redirected to a printer connected to the client computing device for printing. | 10-09-2008 |
Vikram K. Daga, Amherst, MA US
| Patent application number | Description | Published |
|---|---|---|
| 20110086985 | INDUCED POLYMER ASSEMBLIES - The invention provides compositions and methods for inducing and enhancing order and nanostructures in block copolymers and surfactants by certain nonpolymeric additives, such as nanoparticles having an inorganic core and organic functional groups capable of hydrogen bonding. Various compositions having lattice order and nanostructures have been made from a variety of copolymers or surfactants that are mixed with nonpolymeric additives. Particularly, a variety of nanoparticles with an inorganic core and organic functional groups have been discovered to be effective in introducing or enhancing the degree of orders and nanostructures in diverse block copolymers and surfactants. | 04-14-2011 |