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Daga
Jean Michel Daga, Pynier FR
| Patent application number | Description | Published |
|---|---|---|
| 20090210774 | ERROR DETECTING/CORRECTING SCHEME FOR MEMORIES - A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR Flash Memory having differing read/write operations of reading on a per word basis and writing on a per page basis. Advantageously, benefits of the various implementations include reduced encoder/decoder complexities, reduced parity overhead requirements, and reduced performance degradation. | 08-20-2009 |
Jean-Michel Daga, Rousset FR
| Patent application number | Description | Published |
|---|---|---|
| 20110058436 | TECHNIQUES FOR SENSING A SEMICONDUCTOR MEMORY DEVICE - Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a memory cell array comprising a plurality of memory cells. The apparatus may also include a first data sense amplifier circuitry including an amplifier transistor having a first region coupled to at least one of the plurality of memory cells via a bit line. The apparatus may further include a data sense amplifier latch circuitry including a first input node coupled to the data sense amplifier circuitry via a second region of the amplifier transistor. | 03-10-2011 |
Jean-Michel Daga, Peynier FR
| Patent application number | Description | Published |
|---|---|---|
| 20100127752 | LEVEL SHIFTER WITH LOW VOLTAGE DEVICES - A voltage level shifter is disclosed that includes low voltage devices. In some implementations, a voltage level shifter having a differential structure includes low voltage, complementary N-channel metal oxide semiconductor (NMOS) input transistors and low voltage, complementary cross-coupled P-channel metal oxide semiconductor (PMOS) output transistors. One or more complementary NMOS/PMOS series intermediate transistor pairs are interposed between respective drains of the NMOS transistors and PMOS transistors to limit high voltage drops across the NMOS input transistors and PMOS output transistors. In some implementations, each intermediate transistor pair is biased by a single intermediate voltage. The sources of the low voltage devices are connect to a bulk/substrate. The complementary outputs of the level shifter can be taken from the drains of the NMOS/PMOS series intermediate transistor pairs. | 05-27-2010 |
| 20110199848 | TECHNIQUES FOR CONTROLLING A SEMICONDUCTOR MEMORY DEVICE - Techniques for controlling a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a semiconductor memory device including applying a plurality of voltage potentials to a plurality of memory cells arranged in an array of rows and columns. Applying the plurality of voltage potentials to the plurality of memory cells may include applying a first voltage potential to a first memory cell in a row of the array via a first respective bit line and a first switch transistor, applying a second voltage potential to a second memory cell in the row of the array via a second respective bit line and a second switch transistor, and applying a third voltage potential to at least one third memory cell in the row of the array via at least one third respective bit line and at least one third switch transistor, wherein the at least one third memory cell may be located between the first memory cell and the second memory cell in the row of the array. | 08-18-2011 |
Ujjwal Daga, West Bengal IN
| Patent application number | Description | Published |
|---|---|---|
| 20110208928 | System and Method for Improving Performance of Data Container Backups - A method for improving performance of data container backups comprises identifying a data container on a source computer to be backed up. A snapshot image of the data container is generated, wherein the snapshot image comprises one or more partitions. Data is read simultaneously from each of the one or more partitions to a destination computer over one or more transport paths. Each of the one or more transport paths comprises one or more threads. The data read to the destination computer is backed up such that the data retains a physical block sequence of the data container. | 08-25-2011 |