Patent application number | Description | Published |
20080224327 | Microelectronic substrate including bumping sites with nanostructures - A microelectronic substrate and a package including the substrate. The substrate comprises: a wafer; circuitry disposed within the wafer and including a plurality of bonding pads; and a plurality of bumping sites disposed on respective ones of the bonding pads, each of the bumping sites comprising a nanolayer including columnar nanostructures. | 09-18-2008 |
20080225490 | Thermal interface materials - In one embodiment, an apparatus comprises a semiconductor device a heat dissipation assembly, and a thermal interface material disposed between the semiconductor device and the heat dissipation assembly, wherein the thermal interface layer comprises an alloy having a low indium content. | 09-18-2008 |
20080227294 | Method of making an interconnect structure - A method of making an interconnect structure includes providing a die ( | 09-18-2008 |
20080233396 | METHODS OF FORMING CARBON NANOTUBES ARCHITECTURES AND COMPOSITES WITH HIGH ELECTRICAL AND THERMAL CONDUCTIVITIES AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming microelectronic devices are described. Those methods may include method of forming a layered nanotube structure comprising a wetting layer disposed on a nanotube, a Shottky layer disposed on the wetting layer, a barrier layer disposed on the Shottky layer, and a matrix layer disposed on the barrier layer. | 09-25-2008 |
20080233682 | METHODS OF FORMING A CORED METALLIC THERMAL INTERFACE MATERIAL AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a core portion of a TIM, wherein the core portion comprises a high thermal conductivity and does not comprise indium, and forming an outer portion of the TIM on the core portion. | 09-25-2008 |
20080239620 | CARBON NANOTUBE COATED CAPACITOR ELECTRODES - Devices and methods for their formation, including electronic devices containing capacitors, are described. In one embodiment, a device includes a substrate and a capacitor is formed on the substrate. The capacitor includes first and second electrodes and a capacitor dielectric between the first and second electrodes. At least one of the first and second electrodes includes a metal layer having carbon nanotubes coupled thereto. In one aspect of certain embodiments, the carbon nanotubes are at least partially coated with an electrically conductive material. In another aspect of certain embodiments, the substrate comprises an organic substrate and the capacitor dielectric comprises a polymer material. Other embodiments are described and claimed. | 10-02-2008 |
20080311738 | METHOD OF FORMING AN INTERCONNECT JOINT - A method of forming an interconnect joint includes providing a first metal layer ( | 12-18-2008 |
20090001557 | Forming a semiconductor package including a thermal interface material - In one embodiment, the present invention includes a method for placing a thermal interface material (TIM) between a die including a backside metallic (BSM) layer including copper (Cu) and a heat spreader having a contact surface including Cu, where the TIM is formed of an alloy including indium (In) and tin (Sn), and bonding the TIM to the die and the heat spreader to form at least one quaternary intermetallic compound (IMC) layer. Other embodiments are described and claimed. | 01-01-2009 |
20090004500 | MULTILAYER PREFORM FOR FAST TRANSIENT LIQUID PHASE BONDING - In some embodiments, a multilayer preform for fast transient liquid phase bonding is presented. In this regard, a method is introduced consisting of forming a plurality of first alloy layers, forming a plurality of second alloy layers, wherein the second alloy has a melting temperature that is higher than the melting temperature of the first alloy, and placing the first and second alloy layers together in an alternating sequence such that there is one more layer of the first alloy than of the second alloy and that the top and bottom layers of the formation are of the first alloy. Other embodiments are also disclosed and claimed. | 01-01-2009 |
20090032970 | STACKING OF INTEGRATED CIRCUITS USING GLASSY METAL BONDING - Techniques associated with stacking integrated circuits using glassy metal bonding are generally described. In one example, an apparatus includes a first integrated circuit having one or more bonding pads and a second integrated circuit having one or more bonding pads, the second integrated circuit being electrically and mechanically coupled with the first integrated circuit by one or more joints formed between the one or more bonding pads of the first and second integrated circuit using a bulk metallic glass bonding material, wherein the bulk metallic glass material provides a low temperature and low pressure bonding solution to reduce delamination or wherein the bulk metallic glass provides reduced intermetallic compound to increase joint reliability, or suitable combinations thereof. | 02-05-2009 |
20090057378 | IN-SITU CHIP ATTACHMENT USING SELF-ORGANIZING SOLDER - An in-situ chip attachment process uses a self-organizing solder paste composed of a synthetic resin organic flux and solder particles having a mean diameter that falls between around 0.1 μm and around 10 μm. The process is carried out by blanket depositing the solder paste on a first substrate having a first metal structure, pressing a second substrate having a second metal structure into the solder paste such that the second metal structure is aligned with the first metal structure and a gap exists between the first and second metal structures, heating the solder paste to a reflow temperature for a time duration sufficient to cause the solder particles to coalesce and form an electrical connection between the first and second metal structures. The reflow temperature ranges from around 100° C. to around 500° C. The time duration ranges between around 30 seconds and around 900 seconds. | 03-05-2009 |
20090068830 | Microelectronic package interconnect and method of fabrication thereof - A method of interconnecting and an interconnect is provided to connect a first component and a second component of an integrated circuit. The interconnect includes a plurality of Carbon Nanotubes (CNTs), which provide a conducting path between the first component and the second component. The interconnect further includes a passivation layer to fill the gaps between adjacent CNTs. A method of producing Anisotropic Conductive Film (ACF) and an ACF is provided. The ACF includes a plurality of CNTs, which provide a conducting path between a first side of the ACF and a second side of the ACF. The sides of the ACF can also include a conductive curable adhesive layer. In an embodiment, the conductive curable adhesive layer can incorporate a B-stage cross-linkable polymer and silver particles. | 03-12-2009 |
20090128274 | INDUCTOR USING BULK METALLIC GLASS MATERIAL - Inductors using bulk metallic glass (BMG) material and associated methods are generally described. In one example, an apparatus includes an electrically conductive core material, an electrically insulative material coupled with the electrically conductive core material, and a magnetic bulk metallic glass (BMG) material coupled with the electrically insulative material, wherein the electrically conductive core material, the electrically insulative material, and the magnetic BMG material form an inductor. | 05-21-2009 |
20090242121 | LOW STRESS, LOW-TEMPERATURE METAL-METAL COMPOSITE FLIP CHIP INTERCONNECT - In some embodiments, a low stress, low-temperature metal-metal composite flip chip interconnect is presented. In this regard, a method is introduced consisting of combining a powder of substantially pure tin with a powder of tin alloy having a lower melting point than pure tin and depositing the combination of metals between an integrated circuit device and a package substrate. Other embodiments are also disclosed and claimed. | 10-01-2009 |
20090244850 | THERMAL INTERFACE MATERIAL FOR COMBINED REFLOW - A combined thermal interface material and second layer interconnect reflow material and method are disclosed. | 10-01-2009 |
20090321962 | MICROELECTRONIC PACKAGE WITH SELF-HEATING INTERCONNECT - A microelectronic package is provided. The microelectronic package includes a substrate having a plurality of solder bumps disposed on a top side of the substrate and a die disposed adjacent to the top side of the substrate. The die includes a plurality of glassy metal bumps disposed on a bottom side of the die wherein the plurality of glassy metal bumps are to melt the plurality of solder bumps to form a liquid solder layer. The liquid solder layer is to attach the die with the substrate. | 12-31-2009 |
20100037990 | BULK METALLIC GLASS SOLDER MATERIAL - High strength, reliable bulk metallic glass (BMG) solder materials formed from alloys possessing deep eutectics with asymmetric liquidous slopes. BMG solder materials are stronger and have a higher elastic modulus than, and therefore are less likely than crystalline solder materials to damage fragile low k interlayer dielectric (ILD) materials due to thermal stress in materials with different coefficients of thermal expansion (CTE). | 02-18-2010 |
20100039777 | MICROELECTRONIC PACKAGE WITH HIGH TEMPERATURE THERMAL INTERFACE MATERIAL - A microelectronic package is provided. The microelectronic package includes a substrate, a die coupled to a top surface of the substrate and a integrated heat spreader thermally coupled to the die, wherein the integrated heat spreader comprises integrated heat spreader walls. The microelectronic package also includes a thermal interface material disposed between the die and the integrated heat spreader and an underfill material disposed between the integrated heat spreader and the substrate, wherein the underfill material is disposed within gaps between the integrated heat spreader walls, the die and the thermal interface material. | 02-18-2010 |
20100044848 | SOLDER JOINT RELIABILITY IN MICROELECTRONIC PACKAGING - A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni. | 02-25-2010 |
20100065246 | Methods of fabricating robust integrated heat spreader designs and structures formed thereby - Methods and associated structures of forming an indium containing solder material directly on an active region of a copper HIS is enabled. A copper indium containing solder intermetallic is formed on the active region of the IHS. The solder intermetallic improves the solder-TIM integration process for microelectronic packaging applications. | 03-18-2010 |
20100126631 | CARBON NANOTUBES SOLDER COMPOSITE FOR HIGH PERFORMANCE INTERCONNECT - An embodiment of the present invention is an interconnect technique. Carbon nanotubes (CNTs) are prepared. A CNT-solder composite paste is formed containing the CNTs and solder with a pre-defined volume fraction. | 05-27-2010 |
20100177475 | Carbon nanotube coated capacitor electrodes - Devices and methods for their formation, including electronic devices containing capacitors, are described. In one embodiment, a device includes a substrate and a capacitor is formed on the substrate. The capacitor includes first and second electrodes and a capacitor dielectric between the first and second electrodes. At least one of the first and second electrodes includes a metal layer having carbon nanotubes coupled thereto. In one aspect of certain embodiments, the carbon nanotubes are at least partially coated with an electrically conductive material. In another aspect of certain embodiments, the substrate comprises an organic substrate and the capacitor dielectric comprises a polymer material. Other embodiments are described and claimed. | 07-15-2010 |
20100219511 | CARBON NANOTUBE-SOLDER COMPOSITE STRUCTURES FOR INTERCONNECTS, PROCESS OF MAKING SAME, PACKAGES CONTAINING SAME, AND SYSTEMS CONTAINING SAME - A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array is patterned by using a patterned metallic seed layer on the substrate to form the CNT array by chemical vapor deposition. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used. | 09-02-2010 |
20100276474 | METHOD OF FORMING AN INTERCONNECT JOINT - A method of forming an interconnect joint includes providing a first metal layer ( | 11-04-2010 |
20110051376 | SOLDER JOINT RELIABILITY IN MICROELECTRONIC PACKAGING - A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni. | 03-03-2011 |
20110312131 | Forming A Semiconductor Package Including A Thermal Interface Material - In one embodiment, the present invention includes a method for placing a thermal interface material (TIM) between a die including a backside metallic (BSM) layer including copper (Cu) and a heat spreader having a contact surface including Cu, where the TIM is formed of an alloy including indium (In) and tin (Sn), and bonding the TIM to the die and the heat spreader to form at least one quaternary intermetallic compound (IMC) layer. Other embodiments are described and claimed. | 12-22-2011 |
20120148842 | METHODS OF FORMING CARBON NANOTUBES ARCHITECTURES AND COMPOSITES WITH HIGH ELECTRICAL AND THERMAL CONDUCTIVITES AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming microelectronic devices are described. Those methods may include method of forming a layered nanotube structure comprising a wetting layer disposed on a nanotube, a Shottky layer disposed on the wetting layer, a barrier layer disposed on the Shottky layer, and a matrix layer disposed on the barrier layer. | 06-14-2012 |
20130134587 | MICROELECTRONIC PACKAGE WITH SELF-HEATING INTERCONNECT - A microelectronic package is provided. The microelectronic package includes a substrate having a plurality of solder bumps disposed on a top side of the substrate anda die disposed adjacent to the top side of the substrate. The die includes a plurality of glassy metal bumps disposed on a bottom side of the die wherein the plurality of glassy metal bumps are to melt the plurality of solder bumps to form a liquid solder layer. The liquid solder layer is to attach the die with the substrate. | 05-30-2013 |