Patent application number | Description | Published |
20090285015 | PHASE-CHANGE MEMORY DEVICE INCLUDING BIASING CIRCUIT - A memory cell device is provided which includes a substrate, a plurality of unit memory cells connected between a word line and respective bit lines, where each memory cell including a resistance variable element, such a phase-change element, and a diode connected in series between the word line and the respective bit line, and a biasing circuit which applies a biasing voltage to the substrate to decrease a current flow in the word line. | 11-19-2009 |
20090296458 | RESISTANCE VARIABLE MEMORY DEVICE AND METHOD OF WRITING DATA - A method of programming a resistance variable memory cell to a given logic state includes applying a first programming current to the memory cell, executing a verify read of the memory cell by sensing a logic state of the memory cell, and applying a second programming current to the memory cell when the sensed logic state is different than the given logic state, where the second programming current is greater than the first programming current | 12-03-2009 |
20100227438 | RESISTANCE VARIABLE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a resistance variable device includes forming selection devices on a substrate, forming a conductive layer on the selection devices, patterning the conductive layer in a first direction to form conductive patterns spaced apart from each other in the first direction and connecting a pair of adjacent selection devices to each other in the first direction, forming a resistance-variable-material-layer on the conductive patterns, and patterning the resistance-variable-material-layer and the conductive patterns in a second direction to form rows of resistance-variable material extending in the second direction and to form electrodes spaced apart from one another, such that each electrode corresponds to a separate selection device. | 09-09-2010 |
20100271867 | Variable resistive memory device compensating bit line resistance - Provided is a variable resistance memory device. The variable resistance memory device may include first and second memory cells connected to different lengths of bit lines, respectively, and a select circuit, configured to select the first and second memory cells, which is connected to the first and second memory cells through word lines. The select circuit is configured to compensate for a difference of resistances in the different of the lengths of the bit lines. | 10-28-2010 |
20100321981 | VARIABLE RESISTANCE MEMORY DEVICES COMPENSATING FOR WORD LINE RESISTANCE - Memory devices include a row decoder, a first variable resistance memory cell connected to a first bit line and connected to the row decoder by a word line and a second variable resistance memory cell connected to a second bit line and connected to the row decoder by the word line. The memory devices further include a bit line select circuit coupled to the first and second bit lines and configured to compensate for a difference in word line resistance between the row decoder and the respective first and second memory cells. In some embodiments, the bit line select circuit includes first and second transistors configured to selective respective ones of the first and second bit lines and the first and second transistors have different resistances that compensate for the difference in word line resistance. | 12-23-2010 |
20110134687 | RESISTANCE VARIABLE MEMORY DEVICE AND METHOD OF WRITING DATA - A method of programming a resistance variable memory cell to a given logic state includes applying a first programming current to the memory cell, executing a verify read of the memory cell by sensing a logic state of the memory cell, and applying a second programming current to the memory cell when the sensed logic state is different than the given logic state, where the second programming current is greater than the first programming current | 06-09-2011 |
20120248400 | Integrated Circuit Semiconductor Devices Including Channel Trenches And Related Methods Of Manufacturing - An integrated circuit device may include a semiconductor substrate including an active region and a transistor in the active region. The transistor may include first and second spaced apart source/drain regions in the active region of the semiconductor substrate, and a semiconductor channel region between the first and second source/drain regions. The semiconductor channel region may include a plurality of channel trenches therein between the first and second source/drain regions. A gate insulating layer may be provided on the channel region including sidewalls of the plurality of channel trenches, and a gate electrode may be provided on the gate insulating layer so that the gate insulating layer is between the gate electrode and the semiconductor channel region including the plurality of channel trenches. Related methods are also discussed. | 10-04-2012 |
20120314478 | RESISTIVE MEMORY DEVICE AND SENSING MARGIN TRIMMING METHOD THEREOF - A resistive memory device and a sensing margin trimming method are provided. The resistive memory device includes a memory cell array and a trimming circuit. The memory cell array has a plurality of resistive memory cells. The trimming circuit generates a trimming signal according to a characteristic distribution shift value of the resistive memory cells. With the inventive concept, although a characteristic distribution of memory cells is varied, an erroneous read operation is minimized or reduced by securing a sensing margin stably. Accordingly, a fabrication yield of the resistive memory device is bettered. | 12-13-2012 |
20130051123 | RESISTANCE CHANGE MEMORY DEVICE AND CURRENT TRIMMING METHOD THEREOF - A resistance change memory device includes an array of resistance change memory cells, and a writing circuit configured to reset a selected memory cell to a high resistance state by supplying a RESET current to the selected memory cell in the array of resistance change memory cells in a program operation mode, wherein a level of the RESET current depends on a distribution of initial RESET currents for the array of resistance change memory cells. | 02-28-2013 |
20140219014 | Nonvolatile Memory Device and Writing Method Thereof - A writing method of a nonvolatile memory device is provided which receiving data, a target time, and a target resistance value; writing the data at a memory cell; calculating a resistance drift coefficient based on resistance values of the memory cell read on at least two times; calculating a resistance value of the memory cell on the target time using the resistance drift coefficient; and determining whether the resistance value calculated satisfies the target resistance value. | 08-07-2014 |
20140332863 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor device and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an active fin on a substrate; oxidizing a portion of the active fin to form an insulating pattern between the active fin and the substrate; forming a first gate pattern on the substrate, wherein the first gate pattern crosses the active fin; exposing the substrate on both sides of the first gate pattern; and forming source/drain regions on the exposed substrate. | 11-13-2014 |
20140335673 | METHODS OF MANUFACTURING FINFET SEMICONDUCTOR DEVICES USING SACRIFICIAL GATE PATTERNS AND SELECTIVE OXIDIZATION OF A FIN - A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate. | 11-13-2014 |