Patent application number | Description | Published |
20090057864 | INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN OFFSET STACKED CONFIGURATION - A method for manufacturing an integrated circuit package system includes: providing a base package including a first integrated circuit coupled to a base substrate by an electrical interconnect formed on one side; and mounting an offset package over the base package, the offset package electrically coupled to the base substrate via a system interconnect. | 03-05-2009 |
20090152740 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLIP CHIP - An integrated circuit package system includes: mounting a flip chip over a carrier with a non-active side of the flip chip facing the carrier; mounting a substrate over the flip chip; connecting an internal interconnect between the flip chip and the carrier; and encapsulating the flip chip and the internal interconnect over the carrier with the substrate exposed. | 06-18-2009 |
20090212408 | INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES - An integrated circuit package system comprising: providing a package die; and connecting a connector lead having a first connector end with a protruded connection surface and a lowered structure over the package die. | 08-27-2009 |
20090303690 | INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES - An integrated circuit package system includes: providing a package substrate; mounting an interposer chip containing active circuitry over the package substrate; attaching a conductive bump stack having a base bump end and a stud bump end, the base bump end on the interposer chip; connecting a stack connector to the interposer chip and the package substrate; and applying a package encapsulant over the interposer chip, the stack connector, and the conductive bump stack with the stud bump end of the conductive bump stack substantially exposed. | 12-10-2009 |
20100044878 | INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING CAVITY - An integrated circuit package system includes providing a carrier having a first side and a second side; mounting an integrated circuit over the carrier with the first side facing the integrated circuit; attaching an external interconnect to the second side; and forming an encapsulation over the integrated circuit and around the external interconnect with the external interconnect exposed from the encapsulation and with the encapsulation and the second side forming a cavity. | 02-25-2010 |
20100078789 | SEMICONDUCTOR PACKAGE SYSTEM WITH THROUGH SILICON VIA INTERPOSER - A semiconductor package system includes: providing a top package, a through silicon via interposer embedded in the top package; providing a bottom package having a bottom semiconductor die with a top connection adjacent the center active face thereof, a substrate interposer being embedded in the bottom package, the bottom semiconductor die being attached to the substrate interposer; and attaching the top package to the bottom package, the top package having the through silicon via interposer having a via connected to the top connection. | 04-01-2010 |
20100123232 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING AN INTERNAL STRUCTURE PROTRUSION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an internal structure substrate having an internal structure substrate cavity; mounting an internal structure die above the internal structure substrate; encapsulating the internal structure die with an internal structure encapsulation to form an internal structure package; forming an internal structure protrusion in the internal structure encapsulation below the internal structure substrate cavity; mounting the internal structure package above a substrate; and encapsulating the internal structure package above the substrate with an encapsulation. | 05-20-2010 |
20100244217 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED CONFIGURATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a first stack layer including a first device over a first substrate, the first device including a through silicon via; configuring a second stack layer over the first stack layer, the second stack layer including an analog device; configuring a third stack layer over the second stack layer; and encapsulating the integrated circuit packaging system. | 09-30-2010 |
20100279504 | INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING HONEYCOMB MOLDING - A method of manufacture of an integrated circuit package system includes: providing a substrate with a top surface; configuring the top surface to include electrical contacts and an integrated circuit; providing a structure over the substrate with only a honeycomb meshwork of posts contacting the top surface of the substrate; and depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have discrete hollow conduits that expose the electrical contacts. | 11-04-2010 |
20110057308 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a conductive pillar, having substantially parallel vertical sides, in direct contact with the substrate; mounting an integrated circuit to the substrate beside the conductive pillar; and encapsulating the integrated circuit with an encapsulation having a top surface formed for the conductive pillar to extend beyond. | 03-10-2011 |
20110084373 | INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN OFFSET STACKED CONFIGURATION AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: providing a base package including a first integrated circuit coupled to a base substrate by an electrical interconnect formed on one side; and mounting an offset package over the base package, the offset package electrically coupled to the base substrate via a system interconnect. | 04-14-2011 |
20110089552 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system including: forming a top package including: providing a through silicon via interposer having a through silicon via; coupling a stacked integrated circuit die to the through silicon via, and testing a top package; forming a base package including: providing a substrate, coupling a base integrated circuit die to the substrate, and testing a base package; and coupling a stacked interconnect between the top package and the base package. | 04-21-2011 |
20110101512 | Semiconductor Package and Method of Mounting Semiconductor Die to Opposite Sides of TSV Substrate - A semiconductor package has a first conductive via formed through a substrate. The substrate with first conductive via is mounted to a first carrier. A first semiconductor die is mounted to a first surface of the substrate. A first encapsulant is deposited over the first die and first carrier. The first carrier is removed. The first die and substrate with the first encapsulant is mounted to a second carrier. A second semiconductor die is mounted to a second surface of the substrate opposite the first surface of the substrate. A second encapsulant is deposited over the second die. The second carrier is removed. A bump is formed over the second surface of the substrate. A conductive layer can be mounted over the first die. A second conductive via can be formed through the first encapsulant and electrically connected to the first conductive via. The semiconductor packages are stackable. | 05-05-2011 |
20110127662 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKABLE PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package base having an inward base side and an outward base side; mounting a device over the inward base side and connected to the outward base side; connecting a silicon interposer having a through silicon via to the device and having an external side facing away from the device; and applying an encapsulant around the device, over the package base, and over the silicon interposer with the external side substantially exposed, the encapsulant having a protrusion over the outward base side. | 06-02-2011 |
20110180935 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a conductive pillar, having substantially parallel vertical sides, in direct contact with the substrate; mounting an integrated circuit to the substrate beside a conductive pillar location; and encapsulating the integrated circuit with an encapsulation having a top surface formed for the conductive pillar to extend beyond. | 07-28-2011 |
20110254146 | Semiconductor Device and Method of Forming Electrical Interconnection Between Semiconductor Die and Substrate with Continuous Body of Solder Tape - A semiconductor device has a flipchip type semiconductor die with contact pads and substrate with contact pads. A flux material is deposited over the contact pads of the semiconductor die and contact pads of the substrate. A solder tape formed as a continuous body of solder material with a plurality of recesses is disposed between the contact pads of the semiconductor die and substrate. The solder tape is brought to a liquidus state to separate a portion of the solder tape outside a footprint of the contact pads of the semiconductor die and substrate under surface tension and coalesce the solder material as an electrical interconnect substantially within the footprint of the contact pads of the semiconductor die and substrate. The contact pads on the semiconductor die and substrate can be formed with an extension or recess to increase surface area of the contact pads. | 10-20-2011 |
20110260316 | Semiconductor Device and Method of Forming Bump on Substrate to Prevent ELK ILD Delamination During Reflow Process - A semiconductor device has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer. | 10-27-2011 |
20110291264 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a semiconductor wafer having a chip pad; attaching a wafer frame to the semiconductor wafer, the wafer frame having a horizontal cover integral to a protruding connector with the protruding connector on the chip pad; forming an underfill around the protruding connector and between the horizontal cover and the semiconductor wafer; removing the horizontal cover exposing the underfill and the protruding connector; and singulating an integrated circuit package from the semiconductor wafer. | 12-01-2011 |
20110312133 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND UNDERFILL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a dispense port; attaching an integrated circuit to the package carrier and over the dispense port; placing a mold chase over the integrated circuit and on the package carrier, the mold chase having a hole; and forming an encapsulation through the dispense port or the hole, the encapsulation surrounding the integrated circuit including completely filled in a space between the integrated circuit and the package carrier, and in a portion of the hole, the encapsulation having an elevated portion or a removal surface resulting from the elevated portion detached. | 12-22-2011 |
20120012990 | Semiconductor Device and Method of Forming Protective Layer Over Exposed Surfaces of Semiconductor Die - A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. A shielding layer is formed between the first and second semiconductor die. An electrical interconnect, such as conductive pillar, bump, or bond wire, is formed between the first and second semiconductor die. A conductive TSV can be formed through the first and second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and electrical interconnect. A heat sink is formed over the second semiconductor die. An interconnect structure, such as a bump, can be formed over the second semiconductor die. A portion of a backside of the first semiconductor die is removed. A protective layer is formed over exposed surfaces of the first semiconductor die. The protective layer covers the exposed backside and sidewalls of the first semiconductor die. | 01-19-2012 |
20120025374 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUNDED INTERCONNECT - An integrated circuit packaging system includes: a package carrier; an integrated circuit attached to the package carrier; a rounded interconnect on the package carrier; and an encapsulation over the package carrier covering the integrated circuit and exposing the rounded interconnect having a characteristic free of denting. | 02-02-2012 |
20120032340 | Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV - A semiconductor device has a TSV wafer and semiconductor die mounted over the TSV wafer. A channel is formed through the TSV wafer. An encapsulant is deposited over the semiconductor die and TSV wafer. Conductive TMV are formed through the encapsulant over the conductive TSV and contact pads of the semiconductor die. The conductive TMV can be formed through the channel. A conductive layer is formed over the encapsulant and electrically connected to the conductive TMV. The conductive TMV are formed during the same manufacturing process. An insulating layer is formed over the encapsulant and conductive layer. A plurality of semiconductor die of the same size or different sizes can be stacked over the TSV wafer. The plurality of semiconductor die can be stacked over opposite sides of the TSV wafer. An internal stacking module can be stacked over the semiconductor die and electrically connected through the conductive TMV. | 02-09-2012 |
20120068319 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACK INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate. | 03-22-2012 |
20120104624 | Semiconductor Device and Method of Stacking Semiconductor Die in Mold Laser Package Interconnected by Bumps and Conductive Vias - A semiconductor wafer contains a plurality of first semiconductor die. The semiconductor wafer is mounted to a carrier. A channel is formed through the semiconductor wafer to separate the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. An encapsulant is deposited over the carrier and first semiconductor die and into the channel while a side portion and surface portion of the second semiconductor die remain exposed from the encapsulant. A first conductive via is formed through the encapsulant in the channel. A second conductive via is formed through the encapsulant over a contact pad of the first semiconductor die. A conductive layer is formed over the encapsulant between the first and second conductive vias. An insulating layer is formed over the conductive layer and encapsulant. The carrier is removed. An interconnect structure is formed over the first conductive via. | 05-03-2012 |
20120119345 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DEVICE MOUNT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a base bottom side and a base top side; mounting an integrated circuit perpendicular to the base top side, the integrated circuit having a first conductor partially exposed at a first end facing and connected to the base top side; and forming an encapsulation over the integrated circuit. | 05-17-2012 |
20120146229 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a package substrate bottom side, a package substrate top side, and a package substrate window; mounting a base integrated circuit over the package substrate, the base integrated circuit having a base inactive side and a base active side facing the package substrate top side; attaching a lower internal connector to the base active side and the package substrate bottom side, the lower internal connector through the package substrate window; forming an upper insulation conformal to the base integrated circuit and the package substrate top side, the upper insulation having an upper insulation top side; and forming a peripheral through-insulation connector through the upper insulation, the peripheral through-insulation connector having a peripheral connector bottom side directly on the package substrate top side and a peripheral connector top side coplanar with the upper insulation top side. | 06-14-2012 |
20120146235 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming an outer contact pad having an outer pad top side; mounting an integrated circuit above the outer pad top side; forming an encapsulation having an encapsulation top side and an encapsulation bottom side, the encapsulation over the integrated circuit with the encapsulation bottom side coplanar with the outer pad top side; and forming a vertical interconnect through the encapsulation, the vertical interconnect having an interconnect bottom side directly on the outer pad top side and an interconnect top side exposed from the encapsulation. | 06-14-2012 |
20120211892 | Semiconductor Device and Method of Forming WLCSP Structure Using Protruded MLP - A semiconductor device can include a carrier substrate, and a first semiconductor die disposed on a surface of the carrier substrate. An encapsulant can be disposed over the first semiconductor die and the carrier substrate. The semiconductor device can include first vias disposed through the encapsulant as well as second vias disposed through the encapsulant to expose first contact pads. The first contact pads are on upper surfaces of the first semiconductor die. The semiconductor device can include conductive pillars that fill the first vias, and first conductive metal vias (CMVs) that fill the second vias. The conductive pillar can include a first conductive material, and the first CMVs can be in contact with the first contact pads. The semiconductor device can include a conductive layer disposed over the encapsulant. The conductive layer can electrically connect one of the first CMVs with one of the conductive pillars. | 08-23-2012 |
20120211900 | Semiconductor Device and Method of Forming Multi-Layered UBM with Intermediate Insulating Buffer Layer to Reduce Stress for Semiconductor Wafer - A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers. | 08-23-2012 |
20120217629 | Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump - A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via. | 08-30-2012 |
20120228767 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKABLE DEVICES AND A METHOD OF MANUFACTURE THEREOF - An integrated circuit package system includes: providing a package substrate; mounting an interposer chip containing active circuitry over the package substrate; attaching a conductive bump stack having a base bump end and a stud bump end, the base bump end on the interposer chip; connecting a stack connector to the interposer chip and the package substrate; and applying a package encapsulant over the interposer chip, the stack connector, and the conductive bump stack with the stud bump end of the conductive bump stack substantially exposed. | 09-13-2012 |
20120235307 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME STACKING MODULE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit die having an active side and a passive side; providing a contact pad having a top side oriented in a same direction as the passive side; connecting an inner bond wire to the contact pad and the integrated circuit die; and molding a stacking structure around the contact pad, the inner bond wire, and the integrated circuit die with the passive side and the top side exposed, and the stacking structure having a top structure surface on top and adjacent to or below the integrated circuit die, and a horizontal member under the integrated circuit die and forming a cavity. | 09-20-2012 |
20120241979 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STEP MOLD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; connecting an integrated circuit die to the substrate, with the integrated circuit die having peripheral sides; molding a step mold covering one of the peripheral sides; attaching an intermediate die directly over the integrated circuit die, offset to one of the peripheral sides adjacent to the step mold; and directly connecting the intermediate die to the substrate. | 09-27-2012 |
20120273937 | Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer Layer - A semiconductor device has a substrate with a plurality of contact pads. A first insulation layer is formed over the substrate and contact pads. A portion of the first insulating layer is removed to form a toroid-shaped SRO over the contact pads while retaining a central portion of the first insulating layer over the contact pads. The central portion of the first insulating layer can extend above a surface of the first insulating layer outside the first conductive layer. A first conductive layer is formed over the central portion of the first insulating layer and through the SRO in the first insulating layer over the contact pads. The first conductive layer may extend above a surface of the first insulating layer outside the second conductive layer. A semiconductor die is mounted to the substrate with the bumps electrically connected to the first conductive layer. | 11-01-2012 |
20120273938 | Semiconductor Device and Method of Forming an Interconnect Structure with Conductive Material Recessed Within Conductive Ring Over Surface of Conductive Pillar - A semiconductor device has a semiconductor die with a first conductive layer formed over an active surface of the semiconductor die. An insulation layer is formed over the active surface of the semiconductor die. A second conductive layer is conformally applied over the insulating layer and first conductive layer. Conductive pillars are formed over the first conductive layer. Conductive rings are formed around a perimeter of the conductive pillars. A conductive material is deposited over the surface of the conductive pillars within the conductive rings. A substrate has a third conductive layer formed over a surface of the substrate. The semiconductor die is mounted to a substrate with the third conductive layer electrically connected to the conductive material within the conductive rings. The conductive rings inhibit outward flow of the conductive material from under the conductive pillars to prevent electrical bridging between adjacent conductive pillars. | 11-01-2012 |
20120280374 | Semiconductor Device and Method of Mounting Cover to Semiconductor Die and Interposer with Adhesive Material - A semiconductor device has an interposer with a die attach area interior to the interposer and cover attach area outside the die attach area. A channel is formed into a surface of the interposer within the cover attach area. A dam material is formed over the surface of the interposer within the cover attach area between the channel and edge of the interposer. A semiconductor die is mounted to the die attach area of the interposer. An adhesive material is deposited in the cover attach area away from the channel and dam material. A cover, such as a heat spreader or shielding layer, is mounted to the die and interposer within the cover attach area. The cover presses the adhesive material into the channel and against the dam material to control outward flow of the adhesive material. Alternatively, ACF can be formed over the interposer to mount the cover. | 11-08-2012 |
20120286407 | Semiconductor Device and Method of Forming Leadframe with Conductive Bodies for Vertical Electrical Interconnect of Semiconductor Die - A semiconductor device has a semiconductor die mounted to a substrate. A leadframe has a base plate and integrated tie bars and conductive bodies. The tie bars include a down step with an angled surface and horizontal surface between the conductive bodies. The leadframe is mounted to the semiconductor die and substrate with the base plate disposed on a back surface of the semiconductor die and the conductive bodies disposed around the semiconductor die and electrically connected to the substrate. An encapsulant is deposited over the substrate and semiconductor die and into the down step of the tie bars. A conductive layer is formed over the conductive bodies to inhibit oxidation. The leadframe is singulated through the encapsulant in the down step and through the horizontal portion of the tie bars to electrically isolate the conductive bodies. A semiconductor package can be mounted to the substrate and semiconductor die. | 11-15-2012 |
20120299174 | Semiconductor Device and Method of Stacking Semiconductor Die in Mold Laser Package Interconnected By Bumps and Conductive Vias - A semiconductor wafer contains a plurality of first semiconductor die. The semiconductor wafer is mounted to a carrier. A channel is formed through the semiconductor wafer to separate the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. An encapsulant is deposited over the carrier and first semiconductor die and into the channel while a side portion and surface portion of the second semiconductor die remain exposed from the encapsulant. A first conductive via is formed through the encapsulant in the channel. A second conductive via is formed through the encapsulant over a contact pad of the first semiconductor die. A conductive layer is formed over the encapsulant between the first and second conductive vias. An insulating layer is formed over the conductive layer and encapsulant. The carrier is removed. An interconnect structure is formed over the first conductive via. | 11-29-2012 |
20120306097 | Semiconductor Device and Method of Forming WLCSP Structure using Protruded MLP - A semiconductor device can include a carrier substrate, and a first semiconductor die disposed on a surface of the carrier substrate. An encapsulant can be disposed over the first semiconductor die and the carrier substrate. The semiconductor device can include first vias disposed through the encapsulant as well as second vias disposed through the encapsulant to expose first contact pads. The first contact pads are on upper surfaces of the first semiconductor die. The semiconductor device can include conductive pillars that fill the first vias, and first conductive metal vias (CMVs) that fill the second vias. The conductive pillar can include a first conductive material, and the first CMVs can be in contact with the first contact pads. The semiconductor device can include a conductive layer disposed over the encapsulant. The conductive layer can electrically connect one of the first CMVs with one of the conductive pillars. | 12-06-2012 |
20120306104 | Semiconductor Device and Method of Forming Interconnect Structure With Conductive Pads Having Expanded Interconnect Surface Area for Enhanced Interconnection Properties - A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate. | 12-06-2012 |
20120319266 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND UNDERFILL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a dispense port; attaching an integrated circuit to the package carrier and over the dispense port; placing a mold chase over the integrated circuit and on the package carrier, the mold chase having a hole; and forming an encapsulation through the dispense port or the hole, the encapsulation surrounding the integrated circuit including completely filled in a space between the integrated circuit and the package carrier, and in a portion of the hole, the encapsulation having an elevated portion or a removal surface resulting from the elevated portion detached. | 12-20-2012 |
20120319300 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate with a projection formed along a perimeter of a first surface of the substrate; mounting an integrated circuit over the first surface; forming a protruding interconnect over the first surface between the projection and the integrated circuit; and forming an underfill between the integrated circuit and the projection with a uniform height, the uniform height of the underfill less than a height of the projection. | 12-20-2012 |
20120326291 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a flip chip to the substrate; attaching a heat slug to the substrate and the flip chip; and forming a moldable underfill having a top underfill surface on the substrate, the flip chip, and the heat slug, the moldable underfill having a characteristic of being liquid at room temperature and the top underfill surface over the flip chip. | 12-27-2012 |
20130001773 | Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump - A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via. | 01-03-2013 |
20130032952 | Semiconductor Device and Method of Forming POP With Stacked Semiconductor Die and Bumps Formed Directly on the Lower Die - A semiconductor device has a first semiconductor wafer mounted to a carrier. A second semiconductor wafer is mounted to the first semiconductor wafer. The first and second semiconductor wafers are singulated to separate stacked first and second semiconductor die. A peripheral region between the stacked semiconductor die is expanded. A conductive layer is formed over the carrier between the stacked semiconductor die. Alternatively, a conductive via is formed partially through the carrier. A bond wire is formed between contact pads on the second semiconductor die and the conductive layer or conductive via. An encapsulant is deposited over the stacked semiconductor die, bond wire, and carrier. The carrier is removed to expose the conductive layer or conductive via and contact pads on the first semiconductor die. Bumps are formed directly on the conductive layer and contact pads on the first semiconductor die. | 02-07-2013 |
20130037936 | Semiconductor Device and Method of Forming a Stackable Semiconductor Package with Vertically-Oriented Discrete Electrical Devices as Interconnect Structures - A semiconductor device has a substrate and first semiconductor die to the substrate. A plurality of vertically-oriented discrete electrical devices, such as a capacitor, inductor, resistor, diode, or transistor, is mounted over the substrate in proximity to the first semiconductor die. A first terminal of the discrete electrical devices is connected to the substrate. A plurality of bumps is formed over the substrate adjacent to the discrete electrical devices. An encapsulant is deposited over and between the first semiconductor die and substrate. A portion of the bumps and a second terminal of the discrete electrical devices is exposed from the encapsulant. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. The semiconductor devices are stackable and electrically connected through the substrate, discrete electrical devices, and bumps. A heat spreader or second semiconductor die can be disposed between the stacked semiconductor devices. | 02-14-2013 |
20130056862 | Semiconductor Device and Method of Forming a Low Profile Dual-Purpose Shield and Heat-Dissipation Structure - A semiconductor device has a substrate including a recess and a peripheral portion with through conductive vias. A first semiconductor die is mounted over the substrate and within the recess. A planar heat spreader is mounted over the substrate and over the first semiconductor die. The planar heat spreader has openings around a center portion of the planar heat spreader and aligned over the peripheral portion of the substrate. A second semiconductor die is mounted over the center portion of the planar heat spreader. A third semiconductor die is mounted over the second semiconductor die. First and second pluralities of bond wires extend from the second and third semiconductor die, respectively, through the openings in the planar heat spreader to electrically connect to the through conductive vias. An encapsulant is deposited over the substrate and around the planar heat spreader. | 03-07-2013 |
20130069224 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE UNDERLAYER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a routable layer having a column; mounting an integrated circuit structure in direct contact with the column; and forming a gamma connector to electrically connect the column to the integrated circuit structure. | 03-21-2013 |
20130069240 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE MOLD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a top integrated circuit on a first side of the substrate; mounting a bottom integrated circuit on a second side of the substrate; forming a top encapsulation over the top integrated circuit and a bottom encapsulation over the bottom integrated circuit simultaneously; and forming a bottom via through the bottom encapsulation to the substrate. | 03-21-2013 |
20130075915 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CHIP STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; mounting an integrated circuit structure on the first substrate; mounting a second substrate on the integrated circuit structure; coupling a vertical chip to the first substrate and to the second substrate; and forming a package body for encapsulating the integrated circuit structure, the vertical chip, and a portion of the second substrate. | 03-28-2013 |
20130075916 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXTERNAL WIRE CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package carrier; mounting an integrated circuit to the package carrier; forming an external wire on the package carrier and adjacent to the integrated circuit; forming an encapsulation on the package carrier over the external wire; and forming a hole in the encapsulation with the external wire and a portion of the package carrier exposed from the encapsulation. | 03-28-2013 |
20130075926 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; applying a molded under-fill on the base substrate; forming a substrate contact extender through the molded under-fill and in direct contact with the base substrate; mounting a stack device over the molded under-fill; attaching a coupling connector from the substrate contact extender to the stack device; and forming a base encapsulation on the stack device, the substrate contact extender, and encapsulating the coupling connector. | 03-28-2013 |
20130087913 | Semiconductor Device and Method of Forming Bump on Substrate to Prevent ELK ILD Delamination During Reflow Process - A semiconductor device that has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer. | 04-11-2013 |
20130105963 | Semiconductor Device and Method of Forming Thermal Interface Material and Heat Spreader Over Semiconductor Die | 05-02-2013 |
20130113118 | Semiconductor Device and Method of Forming Sloped Surface in Patterning Layer to Separate Bumps of Semiconductor Die from Patterning Layer - A semiconductor device has a semiconductor die with bumps formed over a surface of the semiconductor die. A conductive layer is formed over a substrate. A patterning layer is formed over the substrate and conductive layer. A masking layer having an opaque portion and linear gradient contrast portion is formed over the patterning layer. The linear gradient contrast portion transitions from near transparent to near opaque. The patterning layer is exposed to ultraviolet light through the masking layer. The masking layer is removed and a portion of the patterning layer is removed to form an opening having a sloped surface to expose the conductive layer. The sloped surface in patterning layer can be formed by laser direct ablation. The semiconductor die is mounted to the substrate with the bumps electrically connected to the conductive layer and physically separated from the patterning layer. | 05-09-2013 |
20130154078 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SLUG AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; mounting a conductive connector over the package carrier; forming an encapsulation over the integrated circuit, the encapsulation having a recess exposing the conductive connector; and mounting a heat slug over the encapsulation, the heat slug having an opening with an opening width greater than a recess width of the recess, the opening exposing a portion of a top surface of the encapsulation. | 06-20-2013 |
20130154085 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT CONDUCTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; mounting a lid base over the substrate, the lid base having a base indentation and a hole with the integrated circuit within the hole; and mounting a heat slug over the lid base, the heat slug having a slug non-horizontal side partially within the base indentation. | 06-20-2013 |
20130154090 | Semiconductor Device and Method of Forming Interconnect Structure with Conductive Pads Having Expanded Interconnect Surface Area for Enhanced Interconnection Properties - A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate. | 06-20-2013 |
20130154107 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COUPLING FEATURES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a wafer substrate having an active side containing a contact; forming a through silicon via extending through the wafer substrate electrically connected to the contact having a via width; forming a first coupling feature extending from a top side of the through silicon via; and forming a second coupling feature on the side of the through silicon via opposite the first coupling feature. | 06-20-2013 |
20130154116 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PERIMETER ANTIWARPAGE STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system comprising: providing a package carrier; mounting an integrated circuit to the package carrier; and forming a perimeter antiwarpage structure on and along a perimeter of the package carrier. | 06-20-2013 |
20130157418 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base carrier; forming a conductive post on the base carrier, the conductive post having a top protrusion with a protrusion top side; mounting a base integrated circuit over the base carrier; and forming a base encapsulation over the base integrated circuit, the base encapsulation having an encapsulation top side and an encapsulation recess with the conductive post partially exposed within the encapsulation recess, the encapsulation top side above the protrusion top side. | 06-20-2013 |
20130221543 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a base integrated circuit over the base substrate; attaching a lead to the base integrated circuit and the base substrate, the lead having a lead attachment portion over the base integrated circuit; and forming a base encapsulation over the lead, the base encapsulation having a cavity exposing the lead attachment portion. | 08-29-2013 |
20130241039 | Semiconductor Device and Method of Mounting Cover to Semiconductor Die and Interposer with Adhesive Material - A semiconductor device has an interposer with a die attach area interior to the interposer and cover attach area outside the die attach area. A channel is formed into a surface of the interposer within the cover attach area. A dam material is formed over the surface of the interposer within the cover attach area between the channel and edge of the interposer. A semiconductor die is mounted to the die attach area of the interposer. An adhesive material is deposited in the cover attach area away from the channel and dam material. A cover, such as a heat spreader or shielding layer, is mounted to the die and interposer within the cover attach area. The cover presses the adhesive material into the channel and against the dam material to control outward flow of the adhesive material. Alternatively, ACF can be formed over the interposer to mount the cover. | 09-19-2013 |
20130241053 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND MOLDED CAVITIES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a conductive post on the substrate, the conductive post includes a vertical side; attaching an integrated circuit to the substrate; and forming an encapsulant including a molded cavity, the vertical side circumscribed by and exposed within the molded cavity from the encapsulant. | 09-19-2013 |
20130264705 | Semiconductor Device and Method of Forming Bump on Substrate to Prevent ELK ILD Delamination During Reflow Process - A semiconductor device that has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer. | 10-10-2013 |
20130299973 | Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV - A semiconductor device has a TSV wafer and semiconductor die mounted over the TSV wafer. A channel is formed through the TSV wafer. An encapsulant is deposited over the semiconductor die and TSV wafer. Conductive TMV are formed through the encapsulant over the conductive TSV and contact pads of the semiconductor die. The conductive TMV can be formed through the channel. A conductive layer is formed over the encapsulant and electrically connected to the conductive TMV. The conductive TMV are formed during the same manufacturing process. An insulating layer is formed over the encapsulant and conductive layer. A plurality of semiconductor die of the same size or different sizes can be stacked over the TSV wafer. The plurality of semiconductor die can be stacked over opposite sides of the TSV wafer. An internal stacking module can be stacked over the semiconductor die and electrically connected through the conductive TMV. | 11-14-2013 |
20130299995 | Semiconductor Device and Method of Depositing Underfill Material With Uniform Flow Rate - A semiconductor device has a substrate and insulating layer formed over a surface of the substrate. A first conductive layer is formed over the surface of the substrate. A second conductive layer is formed over an opposing surface of the substrate. A conductive via is formed through the substrate. An opening is formed in the insulating layer while leaving the first conductive layer intact. The opening narrows with a non-linear side or linear side. The opening can have a rectangular shape. A semiconductor die is mounted over the surface of the substrate. An underfill material is deposited between the semiconductor die and substrate. The opening in the insulating layer reduces a flow rate of the underfill material proximate to the opening. The flow rate of the underfill material proximate to the opening is substantially equal to a flow rate of the underfill material away from the opening. | 11-14-2013 |
20130300004 | Semiconductor Device and Method of Controlling Warpage in Semiconductor Package - A semiconductor device has a substrate. An insulating layer is formed over a surface of the substrate. A semiconductor die is mounted over the surface of the substrate. A channel is formed in the insulating layer around the semiconductor die. An underfill material is deposited between the semiconductor die and the substrate and in the channel. A heat spreader is mounted over the semiconductor die with the heat spreader thermally connected to the substrate. A thermal interface material is formed over the semiconductor die. The underfill material is deposited between the semiconductor die and the substrate along a first edge of the semiconductor die and along a second edge of the semiconductor die opposite the first edge. The channel extends partially through the insulating layer formed over the substrate with the insulating layer maintaining coverage over the substrate within a footprint of the channel. | 11-14-2013 |
20130320519 | Semiconductor Device and Method of Backgrinding and Singulation of Semiconductor Wafer while Reducing Kerf Shifting and Protecting Wafer Surfaces - A semiconductor device has a semiconductor wafer with an interconnect structure formed over a first surface of the wafer. A trench is formed in a non-active area of the semiconductor wafer from the first surface partially through the semiconductor wafer. A protective coating is formed over the first surface and into the trench. A lamination tape is applied over the protective coating. A portion of a second surface of the semiconductor wafer is removed by backgrinding or wafer thinning to expose the protecting coating in the trench. A die attach film is applied over the second surface of the semiconductor wafer. A cut or modified region is formed in the die attach film under the trench using a laser. The semiconductor wafer is expanded to separate the cut or modified region of the die attach film and singulate the semiconductor wafer. | 12-05-2013 |
20130328179 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE PREVENTING MECHANISM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a warpage-compensation zone with a substrate-interior layer exposed from a top substrate-cover, and the warpage-compensation zone having contiguous exposed portion of the substrate-interior layer over corner portions of the package substrate; connecting an integrated circuit die to the package substrate with an internal interconnect; and forming an encapsulation over the integrated circuit die, with the encapsulation directly on the substrate-interior layer in the warpage-compensation zone. | 12-12-2013 |
20130328220 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ASSIST AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming an integrated circuit device having a shaped side; mounting the integrated circuit device on the substrate; forming an encapsulation on the substrate and the integrate circuit device with the shaped side partially exposed from the encapsulation. | 12-12-2013 |
20130334714 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE PREVENTION MECHANISM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes providing a substrate; connecting an integrated circuit die; forming a molding having a temperature-dependent characteristic directly on the top surface of the substrate; and forming a coupling encapsulation having a coupled characteristic different from the temperature-dependent characteristic directly on the molding forms an encapsulation boundary between the coupling encapsulation and the molding. | 12-19-2013 |
20140008783 | Semiconductor Device and Method of Forming Electrical Interconnection Between Semiconductor Die and Substrate with Continuous Body of Solder Tape - A semiconductor device has a flipchip type semiconductor die with contact pads and substrate with contact pads. A flux material is deposited over the contact pads of the semiconductor die and contact pads of the substrate. A solder tape formed as a continuous body of solder material with a plurality of recesses is disposed between the contact pads of the semiconductor die and substrate. The solder tape is brought to a liquidus state to separate a portion of the solder tape outside a footprint of the contact pads of the semiconductor die and substrate under surface tension and coalesce the solder material as an electrical interconnect substantially within the footprint of the contact pads of the semiconductor die and substrate. The contact pads on the semiconductor die and substrate can be formed with an extension or recess to increase surface area of the contact pads. | 01-09-2014 |
20140070410 | Semiconductor Device and Method of Forming Multi-Layered UBM with Intermediate Insulating Buffer Layer to Reduce Stress for Semiconductor Wafer - A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers. | 03-13-2014 |
20140077344 | Semiconductor Device with Protective Layer Over Exposed Surfaces of Semiconductor Die - A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. A shielding layer is formed between the first and second semiconductor die. An electrical interconnect, such as conductive pillar, bump, or bond wire, is formed between the first and second semiconductor die. A conductive TSV can be formed through the first and second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and electrical interconnect. A heat sink is formed over the second semiconductor die. An interconnect structure, such as a bump, can be formed over the second semiconductor die. A portion of a backside of the first semiconductor die is removed. A protective layer is formed over exposed surfaces of the first semiconductor die. The protective layer covers the exposed backside and sidewalls of the first semiconductor die. | 03-20-2014 |
20140110860 | Semiconductor Package and Method of Mounting Semiconductor Die to Opposite Sides of TSV Substrate - A semiconductor device includes a wafer level substrate having a plurality of first conductive vias formed through the wafer level substrate. A first semiconductor die is mounted to the wafer level substrate. A first surface of the first semiconductor die includes contact pads oriented toward a first surface of the wafer level substrate. A first encapsulant is deposited over the first semiconductor die. A second semiconductor die is mounted to the wafer level substrate. A first surface of the second semiconductor die includes contact pads oriented toward a second surface of the wafer level substrate opposite the first surface of the wafer level substrate. A second encapsulant is deposited over the second semiconductor die. A plurality of bumps is formed over the plurality of first conductive vias. A second conductive via can be formed through the first encapsulant and connected to the first conductive via. The semiconductor packages are stackable. | 04-24-2014 |
20140175642 | Semiconductor Device and Method of Forming Interconnect Structure with Conductive Pads Having Expanded Interconnect Surface Area for Enhanced Interconnection Properties - A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate. | 06-26-2014 |
20140264817 | Semiconductor Device and Method of Using Partial Wafer Singulation for Improved Wafer Level Embedded System in Package - A semiconductor device includes a semiconductor wafer including a plurality of first semiconductor die. An opening is formed partially through the semiconductor wafer. A plurality of second semiconductor die is disposed over a first surface of the semiconductor wafer. An encapsulant is disposed over the semiconductor wafer and into the opening leaving a second surface of the semiconductor wafer exposed. A portion of the second surface of the semiconductor wafer is removed to separate the first semiconductor die. An interconnect structure is formed over the second semiconductor die and encapsulant. A thermal interface material is deposited over the second surface of the first semiconductor die. A heat spreader is disposed over the thermal interface material. An insulating layer is formed over the first surface of the semiconductor wafer. A vertical interconnect structure is formed around the first semiconductor die. Conductive vias are formed through the first semiconductor die. | 09-18-2014 |
20140264905 | Semiconductor Device and Method of Forming WLCSP with Semiconductor Die Embedded within Interconnect Structure - A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. An insulating layer is formed over the encapsulant and a first surface of the semiconductor die. A semiconductor component is disposed over the insulating layer and first surface of the semiconductor die. A first interconnect structure is formed over the encapsulant and first surface of the semiconductor die to embed the semiconductor component. A conductive via is formed in the semiconductor die. A heat sink is formed over the semiconductor die. A second interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the semiconductor component. An opening is formed in the insulating layer. | 09-18-2014 |
20140312481 | INTEGRATED CIRCUIT PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stacked integrated circuit package and a method for manufacturing the same are provided. | 10-23-2014 |
20140312512 | Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer Layer - A semiconductor device has a substrate with a plurality of contact pads. A first insulation layer is formed over the substrate and contact pads. A portion of the first insulating layer is removed to form a toroid-shaped SRO over the contact pads while retaining a central portion of the first insulating layer over the contact pads. The central portion of the first insulating layer can extend above a surface of the first insulating layer outside the first conductive layer. A first conductive layer is formed over the central portion of the first insulating layer and through the SRO in the first insulating layer over the contact pads. The first conductive layer may extend above a surface of the first insulating layer outside the second conductive layer. A semiconductor die is mounted to the substrate with the bumps electrically connected to the first conductive layer. | 10-23-2014 |