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Dae-Yong Kim

Dae-Yong Kim, Yongin-Si KR

Patent application number	Description	Published
20090081863	METHOD OF FORMING METAL WIRING LAYER OF SEMICONDUCTOR DEVICE - A method of forming a metal wiring layer of a semiconductor device produces metal wiring that is free of defects. The method includes forming an insulating layer pattern defining a recess on a substrate, forming a conformal first barrier metal layer on the insulating layer pattern, and forming a second barrier metal layer on the first barrier metal layer in such a way that the second barrier metal layer will facilitate the growing of metal from the bottom of the recess such that the metal can fill a bottom part of the recess completely and thus, form damascene wiring. An etch stop layer pattern is formed after the damascene wiring is formed so as to fill the portion of the recess which is not occupied by the damascene wiring.	03-26-2009
20090233439	Method of forming an ohmic layer and method of forming a metal wiring of a semiconductor device using the same - A metal organic precursor represented by a formula of R	09-17-2009
20100237423	SEMICONDUCTOR DEVICES INCLUDING BURIED BIT LINES - A semiconductor device includes a plurality of channel structures on a semiconductor substrate. A bit line groove having opposing sidewalls is defined between sidewalls of adjacent ones of the plurality of channel structures. A plurality of bit lines are formed on corresponding ones of the opposing sidewalls, and the plurality of bit lines are electrically isolated from each other	09-23-2010
20100240184	METHOD OF FORMING BURIED GATE ELECTRODE - A method of forming a buried gate electrode prevents voids from being formed in a silicide layer of the gate electrode. The method begins by forming a trench in a semiconductor substrate, forming a conformal gate oxide layer on the semiconductor in which the trench has been formed, forming a first gate electrode layer on the gate oxide layer, forming a silicon layer on the first gate electrode layer to fill the trench. Then, a portion of the first gate electrode layer is removed to form a recess which exposed a portion of a lateral surface of the silicon layer. A metal layer is then formed on the semiconductor substrate including on the silicon layer. Next, the semiconductor substrate is annealed while the lateral surface of the silicon layer is exposed to form a metal silicide layer on the silicon layer.	09-23-2010
20100240185	Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device includes: forming a trench for forming buried type wires by etching a substrate; forming first and second oxidation layers on a bottom of the trench and a wall of the trench, respectively; removing a part of the first oxidation layer and the entire second oxidation layer; and forming the buried type wires on the wall of the trench by performing a silicide process on the wall of the trench from which the second oxidation layer is removed. As a result, the buried type wires are insulated from each other.	09-23-2010
20110092060	METHODS OF FORMING WIRING STRUCTURES - A semiconductor memory wiring method includes: receiving a substrate having a cell array region and a peripheral circuit region; depositing a first insulating layer on the substrate; forming a first contact plug in the cell array region, the first contact plug having a first conductive material extending through the first insulating layer; forming a first elongated conductive line at substantially the same time as forming the first contact plug, the first elongated conductive line having the first conductive material directly covering and integrated with the first contact plug; forming a second contact plug in the peripheral circuit region at substantially the same time as forming the first contact plug, the second contact plug having the first conductive material extending through the first insulating layer; and forming a second elongated conductive line at substantially the same time as forming the second contact plug, the second elongated conductive line having the first conductive material directly covering and integrated with the second contact plug.	04-21-2011

Dae-Yong Kim, Daejeon-City KR

Patent application number	Description	Published
20100102325	VACUUM CHANNEL TRANSISTOR AND DIODE EMITTING THERMAL CATHODE ELECTRONS, AND METHOD OF MANUFACTURING THE VACUUM CHANNEL TRANSISTOR - Provided are a transistor and a method of manufacturing the transistor, and more particularly, a vacuum channel transistor emitting thermal cathode electrons and a method of manufacturing the vacuum channel transistor. The vacuum channel transistor includes: a motherboard; a micro heater member having a thin-film structure formed on the motherboard; a cathode member having a thin-film structure spaced apart from a center part of the micro heater member by a first interval and formed on the micro heater member; a gate member formed on both outer walls of upper parts of the cathode member; and an anode member spaced apart from the cathode member by a second interval through spacers disposed on the gate member, wherein a vacuum electron passing area is interposed between the cathode member and the anode member by the second interval.	04-29-2010
20110043141	CIRCUIT FOR PREVENTING SELF-HEATING OF METAL-INSULATOR-TRANSITION (MIT) DEVICE AND METHOD OF FABRICATING INTEGRATED-DEVICE FOR THE SAME CIRCUIT - Provided are a MIT device self-heating preventive-circuit that can solve a self-heating problem of a MIT device and a method of manufacturing a MIT device self-heating preventive-circuit integrated device. The MIT device self-heating preventive-circuit includes a MIT device that generates an abrupt MIT at a temperature equal to or greater than a critical temperature and is connected to a current driving device to control the flow of current in the current driving device, a transistor that is connected to the MIT device to control the self-heating of the MIT device after generating the MIT in the MIT device, and a resistor connected to the MIT device and the transistor.	02-24-2011

Dae-Yong Kim, Hwaseong-Si KR

Patent application number	Description	Published
20100103743	Flash memory device and method of testing the flash memory device - A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a plurality of bit lines, a control unit configured to output estimated data and an input/output buffer unit including a plurality of page buffers. Each of the plurality of page buffers corresponds to one of the plurality of bit lines in the memory cell array and is configured to read test data programmed in at least a first page of a memory cell array, compare the read-out test data with the estimated data to determine whether the corresponding bit line is in a pass or failure state and output a test result signal. A voltage of the test result signal is maintained when test data of a second page of the memory cell array is read if the corresponding bit line in the first page is in a failure state.	04-29-2010
20100208526	Non-volatile memory device and method of operation therefor - In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line; and the de-coupling transistor is formed in the well.	08-19-2010

Dae-Yong Kim, Gyeonggi-Do KR

Patent application number	Description	Published
20090191699	METHODS FOR FORMING SILICIDE CONDUCTORS USING SUBSTRATE MASKING - A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers.	07-30-2009

Dae-Yong Kim, Seoul KR

Patent application number	Description	Published
20110182470	MOBILE COMMUNICATION TERMINAL HAVING IMAGE CONVERSION FUNCTION AND METHOD - A mobile communication terminal having an image conversion function arranges and displays area-specific images in a three-dimensional (3D) space on the basis of distance information of the area-specific images of a two-dimensional (2D) image.	07-28-2011