Patent application number | Description | Published |
20080252831 | Color Filter Substrate for Liquid Crystal Display and Method of Fabricating the Same - A color filter substrate for a liquid crystal display and a method of fabricating the same are provided. The color filter substrate for a liquid crystal display includes: light shielding parts formed on a substrate at predetermined intervals to prevent light leakage; color filter Layers disposed between the light shielding parts and including color filter patterns of red (R), green (G) and blue (B) for implementing a color image; and a transparent conductive layer formed on a rear surface of the substrate, on which the color filter layers are formed, and formed in a porous structure having a plurality of holes spaced at predetermined intervals. Therefore, it is possible to shield an electrostatic field due to external static electricity and improve image display quality, thereby increasing high brightness characteristics and readability. | 10-16-2008 |
20110158024 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a bank having a plurality of mats, an address counting unit configured to receive an auto-refresh command consecutively applied at predetermined intervals corresponding to a number of the mats, and sequentially count an internal address in response to the auto-refresh command, and an address transferring unit configured to enable the plurality of mats in response to the auto-refresh command, and transfer the internal address to the plurality of mats at predetermined time intervals. | 06-30-2011 |
20120008423 | SETTING CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A setting circuit includes a selection unit configured to select one of a predefined code and an external code in response to a test signal, and a setting information generation unit configured to generate setting information in response to the code selected by the selection unit. | 01-12-2012 |
20120153280 | INTEGRATED CIRCUIT FOR DETECTING DEFECTS OF THROUGH CHIP VIA - An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode. | 06-21-2012 |
20120272108 | MEMORY AND TEST METHOD FOR MEMORY - A test method for a memory having first and second cell arrays, first compressed data obtained by compressing output data of the first cell array and output data of the second cell array is outputted. When the first compressed data represents that a fail exists, output data of one of the first and second cell arrays is locked as normal data, and second compressed data obtained by compressing the normal data and output data of the other of the first and second cell arrays is outputted. | 10-25-2012 |
20120274358 | IDENTICAL-DATA DETERMINATION CIRCUIT - A identical-data determination circuit includes a first activation unit configured to activate an output signal when first and second signals each have a first level, a second activation unit configured to activate the output signal when the first and second signals each have a second level different from the first level, an initialization unit configured to deactivate the output signal when an initialization signal is applied, and a storage unit configured to store the output signal. | 11-01-2012 |
20120275246 | MULTI-TEST APPARATUS AND METHOD FOR SEMICONDUCTOR CHIPS - An apparatus and method is capable of reducing instantaneously consumed current by allowing write drivers and input buffers not to be simultaneously driven in a multi-test of semiconductor chips. A multi-test apparatus includes an input unit configured to receive data for testing, wherein the data for testing is inputted from a circuit outside of the multi-test apparatus, a plurality of memory banks each including a plurality of memory cells, a plurality of write drivers, corresponding to the respective memory banks, configured to write the test data in the plurality of memory banks, and a write control unit configured to control the plurality of write drivers so that the test data is written in the memory banks in at least two time periods. | 11-01-2012 |
20140368243 | CLOCK PHASE ADJUSTING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A semiconductor device includes a buffer suitable for receiving an input signal, a clock buffer suitable for receiving a clock, a delay locked loop (DLL) suitable for delaying the clock to generate a delay locked clock, a code generation unit suitable for generating a digital code corresponding to 1/N of the clock cycle where N is an integer equal to or more than two, a delay unit suitable for delaying the clock corrected by the DLL by a value corresponding to the digital code to output a delayed clock, and a strobing unit suitable for strobing the input signal using the delayed clock. | 12-18-2014 |