Patent application number | Description | Published |
20130047132 | METHOD OF DESIGNING NONVOLATILE MEMORY DEVICE - In a computer-implemented method of designing a nonvolatile memory device, first parameters associated with external environmental conditions are set. Second parameters associated with structural characteristics and internal environmental conditions are set. A first initial operation condition associated with an erase operation is determined based on the first and second parameters. A second initial operation condition associated with a program operation is determined based on the first and second parameters and the first initial operation condition. A final operation condition associated with reliability is determined based on the first and second parameters, and the first and second initial operation condition. | 02-21-2013 |
20140110786 | SEMICONDUCTOR DEVICE HAVING BURIED CHANNEL ARRAY - A semiconductor device includes a field regions in a substrate to define active regions, gate trenches including active trenches disposed across the active region and field trenches in the field regions, and word lines that fill the gate trenches and extend in a first direction. The word lines include active gate electrodes occupying the active trenches, and field gate electrodes occupying the field trenches. The bottom surface of each field gate electrode, which is disposed between active regions that are adjacent to each other and have one word line therebetween, is disposed at a higher level than the bottom surfaces of the active gate electrodes. | 04-24-2014 |
20140133254 | TEST METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR TEST APPARATUS - A test method of a semiconductor device and a semiconductor test apparatus. The test method includes providing a semiconductor device including a substrate having an active region and an isolation region, a volatile device cell including a gate insulation layer and a gate on the active region, a junction region in the active region, a capacitor connected to the junction region, and a passing gate on the isolation region, providing a first test voltage to the gate and a second test voltage greater than the first test voltage to the passing gate to deteriorate interfacial defects of the gate insulation layer, and measuring retention characteristics of the volatile device cell. | 05-15-2014 |
20140362637 | MEMORY DEVICE, MEMORY SYSTEM, AND OPERATION METHOD THEREOF - A memory device comprises: a memory cell array comprising first and second word lines located adjacent to each other, a first memory cell connected to the first word line, and a second memory cell connected to the second word line and located adjacent to the first memory cell; and a word line voltage supplying unit that transitions a word line voltage of the first word line from a first word line voltage to a second word line voltage, in response to a first control signal. A transition control unit generates the first control signal for controlling a pulse of the word line voltage of the first word line in a transition period from the first word line voltage to the second word line voltage in such a way that a transition waveform profile from the first word line voltage to the second word line voltage is different from a transition waveform profile from the second word line voltage to the first word line voltage. | 12-11-2014 |
20150115345 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A vertical memory device includes a channel, a conductive pattern, gate electrodes, a bit line and a conductive line. A plurality of the channels and the conductive patterns extend in a vertical direction from a top surface of a substrate. The gate electrodes surround outer sidewalls of the channels and the conductive patterns. The gate electrodes are stacked in the vertical direction to be spaced apart from each other. The bit line is electrically connected to the channels. The conductive line is electrically connected to the conductive patterns. | 04-30-2015 |
20150263113 | SEMICONDUCTOR DEVICE HAVING BURIED CHANNEL ARRAY - A semiconductor device includes a field regions in a substrate to define active regions, gate trenches including active trenches disposed across the active region and field trenches in the field regions, and word lines that fill the gate trenches and extend in a first direction. The word lines include active gate electrodes occupying the active trenches, and field gate electrodes occupying the field trenches. The bottom surface of each field gate electrode, which is disposed between active regions that are adjacent to each other and have one word line therebetween, is disposed at a higher level than the bottom surfaces of the active gate electrodes. | 09-17-2015 |