| Patent application number | Description | Published |
|---|
| 20080209150 | NON-VOLATILE MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A method of driving a non-volatile memory device includes supplying power to the memory device, in which setting information related to setting an operating environment is copied and stored in multiple of regions of a memory cell array. An initial read operation of the memory cell array is performed and initial setting data is determined based on the initial read operation. The operating environment of the memory device is set based on the initial setting data. Corresponding portions of the stored copies of the setting information are read at the same time. | 08-28-2008 |
| 20080266956 | FLASH MEMORY DEVICE AND METHOD OF CONTROLLING FLASH MEMORY DEVICE - A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, and a controller configured to generate the block select signals in response to a block address. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address. | 10-30-2008 |
| 20090021985 | INTERNAL VOLTAGE GENERATOR AND CONTROL METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE AND SYSTEM INCLUDING THE SAME - An internal voltage of a semiconductor memory device is controlled, where the internal voltage is set according to a reference voltage. The reference voltage is controlled according to first control data to increase the internal voltage to be higher than a target voltage in a power-up operation, and second control data is read. The reference voltage is then controlled according to the second control data to decrease the internal voltage to the target voltage. | 01-22-2009 |
| 20090313423 | MULTI-BIT FLASH MEMORY DEVICE AND METHOD OF ANALYZING FLAG CELLS OF THE SAME - Disclosed is a multi-bit flash memory device which includes a memory cell array and a control circuit. The memory cell array has multiple memory cells and multiple flag cells. The control circuit determines whether the flag cells are programmed, based on a reference corresponding to a read margin of the flag cells, and controls a program operation of the memory cells in response to the determination. | 12-17-2009 |
| 20100148220 | STACK ARRAY STRUCTURE FOR A SEMICONDUCTOR MEMORY DEVICE - In a stack array structure for a semiconductor memory device, a first semiconductor layer includes a plurality of first cell strings, and a second semiconductor including a plurality of second cell strings. Bit-line contact plugs are configured to couple a bit-line to two adjacent first cell strings aligned in series in a bit-line direction, and to further couple the bit-line to two adjacent second cell strings respectively located over the two adjacent first cell strings. Common source line contact plugs are configured to couple a common source line to the two adjacent first cell strings and the two adjacent second cell strings. Pocket p-well contact plugs are located at positions corresponding to a layout of the bit-line plugs and/or common source line plugs, and are configured to couple a pocket p-well line to the first semiconductor layer and the second semiconductor layer. | 06-17-2010 |
| 20100202216 | NON-VOLATILE MEMORY DEVICE AND SYSTEM HAVING REDUCED BIT LINE BIAS TIME - A non-volatile memory device and system are provided. The non-volatile memory device including; a memory cell array of memory blocks, and a bit line bias block connected to the bit lines and configured to precharge the bit lines, a page buffer precharging the plurality of bit lines and sensing data stored in the memory block via the bit lines, and a controller controlling the bit line bias block to simultaneously precharge the bit lines with the page buffer, thereby reducing the bit line bias time. | 08-12-2010 |
| 20100259982 | FLASH MEMORY DEVICE AND METHOD OF CONTROLLING FLASH MEMORY DEVICE - A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, a controller configured to generate the block select signals in response to a block address and to generate a flag signal when the block address corresponds to a bad block, and an output buffer configured to output fixed data in response to the flag signal indicating that the block address corresponds to the bad block. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address. | 10-14-2010 |
| 20110075484 | NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM EMPLOYING SAME - A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor through the first dummy memory cell and the second dummy memory cell. During a read-out operation mode, a dummy read-out voltage is applied to a first dummy wordline coupled to the first dummy memory cell, and to a second dummy wordline coupled to the second dummy memory cell. The dummy read-out voltage has a lower magnitude than a read-out voltage applied to an unselected memory cell during the read-out operation mode. | 03-31-2011 |
