Patent application number | Description | Published |
20090156036 | MULTIMEDIA CABLE - A multimedia cable includes a casing, a terminal pin, an audio signal unit, a video signal unit, and a control lever. The terminal pin is mounted to the casing so as to be rotated with respect to a rotary shaft, and is configured such that first and second four-conductor terminals are arranged on respective sides of the rotary shaft. A audio signal unit comprising three-conductor connection pins each one end of which is rotatably mounted in the casing and audio cables each of which is connected with said each one end of the three-conductor connection pins respectively. A video signal unit comprising four-conductor connection pins mounted opposite the three-conductor connection pins, each one end of which is rotatably mounted in the casing and video cables which are connected with said each one end of the four-conductor connection pins. The control lever is connected to both the three-conductor connection pins and the four-conductor connection pins to connect either the three-conductor connection pins or the four-conductor connection pins to the terminal pin. | 06-18-2009 |
20110124389 | MILEAGE GAME SYSTEM FOR RUNNING VEHICLE AND METHOD THEREOF - The present invention features, in part, a mileage game system for a running vehicle and a method thereof are disclosed. In preferred embodiments, the mileage game system includes an operation unit enabling a driver to select a mileage game, and generating mileage game data that has an influence on a gas efficiency; a data collecting unit collecting the mileage game data by using a CAN communication; a data processing unit computing a mileage game score from the mileage game data according to a mileage game program previously installed, and calculating the total score of the mileage game scores reflected by the generated mileage game score; and a display screen displaying the total score of the calculated mileage game scores. | 05-26-2011 |
Patent application number | Description | Published |
20090085624 | FLIP-FLOP CIRCUIT AND DUTY RATIO CORRECTION CIRCUIT USING THE SAME - A flip-flop circuit includes a first unit configured to receive a reference clock signal and a reset signal, and a second unit configured to change an output node to a first level in response to the reference clock signal and change the output node to a second level by precharging the output node in response to a signal output from the first unit according to the reset signal. | 04-02-2009 |
20090128208 | APPARATUS AND METHOD FOR DETECTING DUTY RATIO OF SIGNALS IN SEMICONDUCTOR DEVICE CIRCUIT - Apparatus for detecting duty ratio of signals in semiconductor device circuit includes a circuit for detecting a duty ratio of signals in a semiconductor device includes a comparing unit which compares a duty cycle of first and second input clock signals input differentially and generates a first output signal and a second output signal, a latching unit which stores the first and second output signals and generates a detected signal corresponding to the first and second output signals, and an adjusting unit which receives the first and the second output signals, and transmits the first and the second output signals to the latching unit based on a voltage level difference of the first and second output signals. | 05-21-2009 |
20090168944 | LOW PASS FILTER AND LOCK DETECTOR CIRCUIT - A low pass filter includes a driver unit configured to output a voltage proportional to an input pulse width, a charge/discharge unit configured to charge the output voltage of the driver unit, a comparator unit configured to compare an output voltage of the charge/discharge unit with a reference value to output a square wave signal, and a switching unit configured to switch the charge/discharge unit to an operation state, based on a bandwidth expansion signal. | 07-02-2009 |
20090256610 | Quadrature phase correction circuit - A quadrature phase correction circuit includes an N-bit code counter configured to generate an N-bit code value according to a detected phase difference when a quadrature phase correction is carried out; a storage configured to store N-bit code values according to a plurality of detected phase differences; and a controller configured to share the N-bit code counter, control the generation of the N-bit code values according to the plurality of detected phase differences, and control the storing of the N-bit code values in an allocated space of the storage. | 10-15-2009 |
20090278577 | SEMICONDUCTOR DEVICE INCLUDING PHASE DETECTOR - A semiconductor device including an edge synchronizer which outputs a synchronized strobe signal generated by synchronizing a transition time point of a strobe signal with clock edges of a main clock or a sub clock, a detector which outputs a phase determination signal indicating a phase difference between the main clock and the sub clock in response to the synchronized strobe signal, and a duty ratio corrector which adjusts a duty ratio of the main clock and the sub clock in response to the phase determination signal. | 11-12-2009 |
20090322394 | RING OSCILLATOR AND MULTI-PHASE CLOCK CORRECTION CIRCUIT USING THE SAME - A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage. | 12-31-2009 |
20100117692 | MULTI-PHASE CLOCK GENERATION CIRCUIT HAVING A LOW SKEW IMPRECISION - A multi-phase clock generation circuit having a low skew imprecision is presented. The circuit includes a phase clock generation block and a phase correction block. The phase clock generation block is configured to generate a plurality of phase clocks having phases different from each other with response to a pair of input clocks. The phase correction block is configured to generate final output interpolated phase clocks in which each has a center phase by adjusted by multiple phase clocks that have adjacent phases. | 05-13-2010 |
20100148842 | MULTI-PHASE CLOCK SIGNAL GENERATING CIRCUIT HAVING IMPROVED PHASE DIFFERENCE AND A CONTROLLING METHOD THEREOF - A multi-phase clock signal generating circuit includes a phase correction block configured to receive multi-phase clock signals and produce a plurality of interpolated phase clock signal groups in which the phases of the multi-phase clock signals are differently controlled. The multi-phase clock signals are out of phase with each other. A clock control block is configured to produce output multi-clock signals by selectively outputting one among the interpolated phase clock signal groups using a digital control signal having a plurality of bits which are produced based on phase differences of the multi-phase clock signals. | 06-17-2010 |
20110181332 | RING OSCILLATOR FOR GENERATING OSCILLATING CLOCK SIGNAL - A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage. | 07-28-2011 |
20140368248 | FLIP-FLOP CIRCUIT AND DUTY RATIO CORRECTION CIRCUIT USING THE SAME - A flip-flop circuit includes a first unit configured to receive a reference clock signal and a reset signal, and a second unit configured to change an output node to a first level in response to the reference clock signal and change the output node to a second level by precharging the output node in response to a signal output from the first unit according to the reset signal. | 12-18-2014 |