Patent application number | Description | Published |
20120119286 | SEMICONDUCTOR DEVICES HAVING VERTICAL CHANNEL TRANSISTORS AND METHODS FOR FABRICATING THE SAME - A semiconductor device has a plurality of vertical channels extending upright on a substrate, a plurality of bit lines extending among the vertical channels, a plurality of word lines which include a plurality of gates disposed adjacent first sides of the vertical channels, respectively, and a plurality of conductive elements disposed adjacent second sides of the vertical channels opposite the first sides. The conductive elements can provide a path to the substrate for charge carriers which have accumulated in the associated vertical channel to thereby mitigate a so-called floating effect. | 05-17-2012 |
20130256793 | SEMICONDUCTOR DEVICES HAVING BIT LINE INSULATING CAPPING PATTERNS AND MULTIPLE CONDUCTIVE PATTERNS THEREON - A semiconductor device capable of reducing a thickness, an electronic product employing the same, and a method of fabricating the same are provided. The method of fabricating a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor in the first active region includes a first gate pattern and first impurity regions. A second transistor the second active region includes a second gate pattern and second impurity regions. A first conductive pattern is on the first transistor, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern. The first conductive pattern may be formed on the first transistor while the second transistor is formed. | 10-03-2013 |
20130299834 | BURIED CHANNEL TRANSISTOR AND METHOD OF FORMING THE SAME - A semiconductor device may include a plurality of memory cells. The memory cells may be formed with respective fin shaped active regions with respective recesses formed therein. Thicknesses of the fins may be made relatively thicker around the recesses, such as by selective epitaxial growth around the recesses. The additional thicknesses may be asymmetrical so that portions of the fin on one side are larger than an opposite side. Related methods and systems are also disclosed. | 11-14-2013 |
20130307068 | MOS TRANSISTORS INCLUDING U SHAPED CHANNELS REGIONS WITH SEPARATED PROTRUDING PORTIONS - A MOS transistor, can include a u-shaped cross-sectional channel region including spaced apart protruding portions separated by a trench and connected to one another by a connecting portion of the channel region at lower ends of the spaced apart protruding portions of the channel region. First and second impurity regions can be located at opposite ends of the -shaped cross-sectional channel region and separated from one another by the trench. A gate electrode can cover at least a planar face of the u-shaped cross-sectional channel region including the spaced apart protruding portions and the connecting portion and exposing the first and second impurity regions. | 11-21-2013 |
20140061736 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a stack structure of a conductive line and an insulating capping line extending in a first direction on a substrate, a plurality of contact plugs arranged in a row along the first direction and having sidewall surfaces facing the conductive line with air spaces between the sidewall surfaces and the conductive line, and a support interposed between the insulating capping line and the contact plugs to limit the height of the air spaces. The width of the support varies or the support is present only intermittently in the first direction. In a method of manufacturing the semiconductor devices, a sacrificial spacer is formed on the side of the stack structure, the spacer is recessed, a support layer is formed in the recess, the support layer is etched to form the support, and then the remainder of the spacer is removed to provide the air spaces. | 03-06-2014 |
20140145268 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes an insulating interlayer over a substrate in a first region, the insulating layer including contact holes exposing a portion of a surface of the substrate, and contact plugs in the contact holes. The contact plugs include a stacked structure of a first barrier metal layer pattern and a first metal layer pattern. The semiconductor device also includes second metal layer patterns directly contacting with the contact plugs and an upper surface of the insulating interlayer. The second metal layer pattern consists is a metal material layer. | 05-29-2014 |
20140154882 | METHODS FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a device isolation layer pattern on a substrate to form an active region, the active region including a first contact forming region at a center p of the active region and second and third contact forming regions at edges of the active region, forming an insulating layer and a first conductive layer on the substrate, forming a mask pattern having an isolated shape on the first conductive layer, etching the first conductive layer and the insulating layer to expose the active region of the first contact forming region by using the mask pattern, to form an opening portion between pillar structures, forming a second conductive layer in the opening, and patterning the second conductive layer and the first preliminary conductive layer pattern to form a wiring structure contacting the first contact forming region and having an extended line shape. | 06-05-2014 |
20140252440 | SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE PLUG - Semiconductor devices include a substrate having a target connection region; a conductive line having a first side wall spaced apart from the substrate by at least an insulating layer, and a conductive plug structure electrically connecting the conductive line to the target connection region, wherein the conductive plug includes a first conductive plug having a first side wall, a bottom surface contacting the target connection region of the substrate, and a second side wall facing the first side wall of the conductive line, and a second conductive plug between the conductive line and the first conductive plug. The second conductive plug contacts both the first side wall of the conductive line and the second side wall of the first conductive plug. | 09-11-2014 |