| Patent application number | Description | Published |
|---|
| 20100023676 | SOLID STATE STORAGE SYSTEM FOR DATA MERGING AND METHOD OF CONTROLLING THE SAME ACCORDING TO BOTH IN-PLACE METHOD AND OUT-OF-PLACE METHOD - A solid state storage system includes a controller configured to divide memory blocks of a flash memory area into first blocks and second blocks corresponding to the first blocks, newly allocates pages of the second blocks when an external write command is requested. The controller is also configured to allocate selected sectors in the allocated pages according to sector addresses and execute a write command. | 01-28-2010 |
| 20100023677 | SOLID STATE STORAGE SYSTEM THAT EVENLY ALLOCATES DATA WRITING/ERASING OPERATIONS AMONG BLOCKS AND METHOD OF CONTROLLING THE SAME - A solid state storage system that evenly allocates data writing/erasing operations among blocks is presented. The solid state storage system includes a controller. The controller is configured to set a representative value that becomes a block allocation reference in accordance with predetermined information of blocks in a flash memory area. The controller is also configured to calculate a data value that becomes life time information according to the predetermined information in a current state for each block. The controller is also configured to determine a block where a deviation is generated between the representative value and the data value. The controller is also configured to allocate block where the deviation is generated as a new block where data is written. | 01-28-2010 |
| 20100030947 | HIGH-SPEED SOLID STATE STORAGE SYSTEM - A solid state storage device includes a main memory cell array and a sub-memory area. The main memory cell array stores data in a flash memory, whereas the sub-memory includes a non-volatile random access memory for storing data. The data storage speed of the non-volatile random access memory of the sub-memory area is faster than the data storage speed of the flash memory of the main memory cell area. The sub-memory area of the solid state storage device also stores address mapping information therein, so that the address mapping information does not have to be transferred to the main memory cell area and a portion of the main memory cell area does not have to be designated for a non-volatile memory for storing the address mapping information. | 02-04-2010 |
| 20100030948 | SOLID STATE STORAGE SYSTEM WITH DATA ATTRIBUTE WEAR LEVELING AND METHOD OF CONTROLLING THE SOLID STATE STORAGE SYSTEM - A solid state storage system is disclosed capable of performing wear leveling utilizing attributes of different types of data. The solid state storage system performs a control operation such that logical addresses are configured to be mapped to physical addresses of pages in multiple planes of a memory area. In addition, the continuous logical addresses are mapped to the physical addresses of the pages of the different planes. The logical addresses are subsequently grouped so as to define multiple data areas for programming data having different attributes. Accordingly, the data is allocated so as to reduce a life time deviation between planes. | 02-04-2010 |
| 20100030953 | HIGH-SPEED SOLID STATE STORAGE SYSTEM HAVING A NON-VOLATILE RAM FOR RAPIDLY STORING ADDRESS MAPPING INFORMATION - A solid state storage system incorporating a non-volatile randome access memory (NVRAM) that exhibits a reduced storage time is presented. The solid state storage system includes a memory area, a controller, and an information storage area. The controller is configured to control the memory area. The information storage area controlled by the controller and is configured to store logical address mapping information and physical address mapping information of the memory area. | 02-04-2010 |
| 20110161611 | METHOD FOR CONTROLLING SEMICONDUCTOR STORAGE SYSTEM CONFIGURED TO MANAGE DUAL MEMORY AREA - A method for controlling a semiconductor storage system configured to manage dual memory areas for protecting the system against abrupt and abnormal power disruptions is presented. The semiconductor storage systems has a first physical area and a second physical area, in which first data having a first logical block address are stored in the first physical area. The method includes providing a write command so that the first data is updated to second data. The method also includes writing the second data in a second physical area in response to the write command. When writing the second data in the second physical area, a corresponding invalid logical address is allocated to the second physical area. | 06-30-2011 |
| 20110161774 | SEMICONDUCTOR MEMORY SYSTEM HAVING ECC CIRCUIT AND METHOD OF CONTROLLING THEREOF - A semiconductor storage system includes: a memory region having a plurality of memory cells; and a memory controller having a data control unit. The data control unit includes a write control unit which, during a write operation, performs first error check correction (ECC) encoding on an input data to generate a first encoded input data, compresses the first encoded input data to generate a compressed input data, and performs second ECC encoding on the compressed input data to generate a second encoded input data. The write control unit then writes the second encoded input data into the memory region as a write data. | 06-30-2011 |
