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Dae-Han
Dae Han Kim, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20090147575 | NOR FLASH MEMORY DEVICE WITH A SERIAL SENSING OPERATION AND METHOD OF SENSING DATA BITS IN A NOR FLASH MEMORY DEVICE - In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed. | 06-11-2009 |
| 20100214843 | NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME - A non-volatile memory device including a cell array having memory cells arranged at intersections of word lines and bit lines; an address decoder configured to select one of the word lines in response to an address; a write circuit configured to write program data in memory cells connected with the selected word line; and a control circuit configured to control the address decoder and the write circuit such that a plurality of band program (write) operations are sequentially executed during a write operation, wherein the control circuit is further configured to select each band write operation the optimal write condition of the next band write operation. A plurality of available write conditions are stored as trim information in a plurality of registers. The control circuit selects the register storing information for performing programming under the optimal write condition. | 08-26-2010 |
| 20100254193 | WIRITING METHOD OF A NONVOLATILE MEMORY DEVICE - A method of performing a writing operation of a nonvolatile memory device is provided. The method includes performing a first band program using trim information from a first band register of multiple band registers, which include at least a default band register; and performing a second band program using trim information from a second band register or trim information from the default band register after performing the first band program. The second band register is selected while the first band program is being performed. | 10-07-2010 |
Dae Han Kwon, Ichon KR
| Patent application number | Description | Published |
|---|---|---|
| 20090045862 | CLOCK GENERATING CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A clock generating circuit of a semiconductor memory apparatus includes a phase splitter that delays a clock to generate a delayed clock and inverts the clock to generate an inverted clock, and a clock buffer that buffers the delayed clock and the inverted clock and outputs a rising clock and a falling clock. | 02-19-2009 |
Dae Han Kwon, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110267112 | OUTPUT DRIVER AND SEMICONDUCTOR APPARATUS HAVING THE SAME - An output driver includes: a pull-up signal generation unit configured to control a pulse width of first data and output a pull-up pre-drive signal; a pull-down signal generation unit configured to control a pulse width of second data and output a pull-down pre-drive signal; a pull-up pre-driver unit configured to receive the pull-up pre-drive signal and generate a pull-up main drive signal; a pull-down pre-driver unit configured to receive the pull-down pre-drive signal and generate a pull-down main drive signal; a pull-up main driver unit configured to charge an output node according to the pull-up main drive signal; and a pull-down main driver unit configured to discharge the output node according to the pull-down main drive signal. | 11-03-2011 |
| 20110267124 | CLOCK SIGNAL DUTY CORRECTION CIRCUIT - A clock signal duty correction circuit includes: a first transition timing control unit configured to generate a first control signal for controlling a rising timing of a duty correction clock signal by using a clock signal; a second transition timing control unit configured to generate a second control signal for varying a falling timing of the duty correction clock signal by using the clock signal according to a code signal; and a differential buffer unit configured to generate the duty correction clock signal, whose rising time or falling time is adjusted, in response to the first control signal and the second control signal. | 11-03-2011 |
Dae-Han Choi, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100148317 | CRITICAL DIMENSION REDUCTION AND ROUGHNESS CONTROL - A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer. | 06-17-2010 |
Dae-Han Kwon, Gyeoggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100061157 | DATA OUTPUT CIRCUIT - A data output circuit includes a serial data output unit for outputting a plurality of parallel data as serial data according to an operation mode, an internal information output unit for outputting internal information data according to the operation mode, and a buffering unit for receiving the serial data and the internal information data through an identical input end and buffering the received data. | 03-11-2010 |
Dae-Han Yoo, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20080305572 | METHOD OF FABRICATING IMAGE DEVICE HAVING CAPACITOR AND IMAGE DEVICE FABRICATED THEREBY - There are provided a method of fabricating an image device having a capacitor and an image device fabricated thereby. The method comprises preparing a substrate having a pixel region and a peripheral circuit region. A lower electrode containing silicon is formed on the substrate of the peripheral circuit region. A capacitor dielectric layer is formed by sequentially stacking a first dielectric layer and a second dielectric layer on the lower electrode, and the first dielectric layer and the second dielectric layer have a different dielectric constant from each other. In this case, one of the first and second dielectric layers is a dielectric layer grown from a material layer formed thereunder and has a lower dielectric constant than that of the other. An upper electrode is formed on the capacitor dielectric layer. | 12-11-2008 |