| Patent application number | Description | Published |
|---|
| 20090242944 | METHOD OF FORMING A SEMICONDUCTOR DEVICE USING STRESS MEMORIZATION - A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film is removed, a second anneal is applied to the semiconductor device sufficiently long and at a sufficiently high temperature to activate dopants implanted for forming device source/drains. The result of this approach is that there is minimal gate dielectric growth in the channel along the border of the channel. | 10-01-2009 |
| 20090289280 | Method for Making Transistors and the Device Thereof - A semiconductor process and apparatus includes forming <100> channel orientation PMOS transistors ( | 11-26-2009 |
| 20090291540 | CMOS Process with Optimized PMOS and NMOS Transistor Devices - A semiconductor process and apparatus includes forming NMOS and PMOS transistors ( | 11-26-2009 |
| 20100019328 | Semiconductor Resistor Formed in Metal Gate Stack - A semiconductor process and apparatus fabricate a metal gate electrode ( | 01-28-2010 |
| 20100078687 | Method for Transistor Fabrication with Optimized Performance - A semiconductor process and apparatus includes forming <100> channel orientation CMOS transistors ( | 04-01-2010 |
| 20100171180 | METHOD FOR PFET ENHANCEMENT - A semiconductor process and apparatus includes forming PMOS transistors ( | 07-08-2010 |
| 20110169096 | BALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERS - An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor. | 07-14-2011 |
| 20110180883 | METHOD AND STRUCTURE TO IMPROVE BODY EFFECT AND JUNCTION CAPACITANCE - A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface of the substrate above the channel region; and implant a second-type impurity within the substrate to form source and drain regions within the substrate adjacent the top surface. The channel region is positioned between the source and drain regions. The second-type impurity has an opposite polarity with respect to the first-type impurity. The method and structure implant a greater concentration of the first-type impurity, relative to a concentration of the first-type impurity within the channel region, to form a primary body doping region within the substrate below (relative to the top surface) the channel region; and to form secondary body doping regions within the substrate below (relative to the top surface) the source and drain regions. | 07-28-2011 |
