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Czysz
Dariusz Czysz, Poznan PL
| Patent application number | Description | Published |
|---|---|---|
| 20100138708 | DECOMPRESSORS FOR LOW POWER DECOMPRESSION OF TEST PATTERNS - Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing. | 06-03-2010 |
| 20100306609 | Low Power Decompression Of Test Cubes - Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing. | 12-02-2010 |
| 20110320999 | DECOMPRESSORS FOR LOW POWER DECOMPRESSION OF TEST PATTERNS - Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing. | 12-29-2011 |
Dariusz Czysz, Ostrow Wielkopolski PL
| Patent application number | Description | Published |
|---|---|---|
| 20100229060 | Compression Based On Deterministic Vector Clustering Of Incompatible Test Cubes - The test data compression scheme is based on deterministic vector clustering. Test cubes that feature many similar specified bits are merged into a parent pattern in the presence of conflicts. The parent pattern along with a control pattern and incremental patterns representing conflicting bits are encoded efficiently. A tri-modal decompressor may be used to decompress the test data. | 09-09-2010 |
| 20110166818 | LOW POWER SCAN TESTING TECHNIQUES AND APPARATUS - Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed. | 07-07-2011 |
Dariusz Czysz US
| Patent application number | Description | Published |
|---|---|---|
| 20110231721 | LOW POWER COMPRESSION OF INCOMPATIBLE TEST CUBES - Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns. | 09-22-2011 |
Darjusz Czysz, Wielkopolski PL
| Patent application number | Description | Published |
|---|---|---|
| 20090300446 | Selective Per-Cycle Masking Of Scan Chains For System Level Test - Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon. | 12-03-2009 |
Michael Czysz, Portland, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20120111650 | Drive System - A drive system package includes a housing. Located at the housing are a mechanical interface to output mechanical power, an electrical power connector receiver and a user interface. A motor vehicle includes a motor vehicle frame and one or more drive components. The motor vehicle further includes a drive system package having a housing. A mechanical interface is located at the housing and is operably connectable to the one or more drive components. The drive system package further includes an electrical power connector receiver and a user interface located at the housing. | 05-10-2012 |