Patent application number | Description | Published |
20110044831 | MOTOR WITH HIGH PRESSURE RATED CAN - An apparatus includes a motor. The motor includes a rotor, a stator disposed around the rotor, and a first high pressure rated can separating the stator from the rotor. The first high pressure rated can at least partially defines a rotor cavity encompassing at least a portion of the rotor and a first pressure environment independent of a second pressure environment of the stator. The second pressure environment of the stator is substantially pressure balanced with respect to the ambient environment. | 02-24-2011 |
20110050017 | METHOD AND APPARATUS FOR CONTROLLING A BEARING THROUGH A PRESSURE BOUNDARY - A rotating apparatus includes a housing, a shaft at least partially disposed within a first pressure environment defined by the housing, a first magnetic bearing supporting the shaft and being at least partially disposed within the first pressure environment, a sensor operable to sense a position of the shaft relative to the first magnetic bearing, a controller disposed in a second pressure environment independent of the first pressure environment and operable to communicate with the sensor and to generate a control signal for the first magnetic bearing based on the sensed position, and a communication device operable to communicate the control signal between the controller and the first magnetic bearing and to communicate the sensed position between the sensor and the controller without penetrating a pressure boundary defined between the first and second pressure environments. | 03-03-2011 |
20110052432 | PUMP WITH MAGNETIC BEARINGS - A pump unit includes a motor, a pump, a shaft spanning the motor and the pump, and at least a first magnetic bearing supporting the shaft. A hydrocarbon production system includes an underwater well and a pump unit exposed to an underwater environment. The pump unit is operable to pump a production fluid from the well and includes a motor, a pump, a shaft spanning the motor and the pump, and at least a first magnetic bearing supporting the shaft. | 03-03-2011 |
20110058965 | IN-LINE FLOW MIXER - A flow-conditioning system includes a pump, process tubing coupling the pump to a source of multiple component process fluid, and an in-line flow-mixing device positioned in the process tubing upstream of the pump. A system includes a well disposed below a body of water and providing a source of multiple component fluid, a pump disposed in and exposed to the water, process tubing coupling the pump to the well, and an in-line flow-mixing device positioned in the process tubing upstream of the pump. | 03-10-2011 |
20110058966 | FLUSHING SYSTEM - An apparatus includes a pump, a motor operatively coupled to the pump, and a flushing system. The motor includes a stator and a rotor disposed in a rotor cavity isolated from the stator. The flushing system is operable to provide a flushing medium to the rotor cavity. | 03-10-2011 |
Patent application number | Description | Published |
20100108370 | SYSTEM AND METHOD OF FORMING A PATTERNED CONFORMAL STRUCTURE - A system and method of forming a patterned conformal structure for an electrical system is disclosed. The conformal structure includes a dielectric coating shaped to conform to a surface of an electrical system, with the dielectric coating having a plurality of openings therein positioned over contact pads on the surface of the electrical system. The conformal structure also includes a patterned conductive coating layered on the dielectric coating and on the contact pads such that an electrical connection is formed between the patterned conductive coating and the contact pads. The patterned conductive coating comprises at least one of an interconnect system, a shielding structure, and a thermal path. | 05-06-2010 |
20100224992 | SYSTEM AND METHOD FOR STACKED DIE EMBEDDED CHIP BUILD-UP - An embedded chip package (ECP) includes a plurality of re-distribution layers joined together in a vertical direction to form a lamination stack, each re-distribution layer having vias formed therein. The embedded chip package also includes a first chip embedded in the lamination stack and a second chip attached to the lamination stack and stacked in the vertical direction with respect to the first chip, each of the chips having a plurality of chip pads. The embedded chip package further includes an input/output (I/O) system positioned on an outer-most re-distribution layer of the lamination stack and a plurality of metal interconnects electrically coupled to the I/O system to electrically connect the first and second chips to the I/O system. Each of the plurality of metal interconnects extends through a respective via to form a direct metallic connection with a metal interconnect on a neighboring re-distribution layer or a chip pad on the first or second chip. | 09-09-2010 |
20100319981 | SYSTEM AND METHOD OF FORMING ISOLATED CONFORMAL SHIELDING AREAS - A system and method of forming a patterned conformal structure for an electrical system is disclosed. The conformal structure includes a dielectric coating positioned on an electrical system having circuit components mounted thereon, the dielectric coating shaped to conform to a surface of the electrical system and having a plurality of openings therein positioned over contact pads on the surface of the electrical system. The conformal structure also includes a conductive coating layered on the dielectric coating and on the contact pads such that an electrical connection is formed between the conductive coating and the contact pads. The dielectric coating and the conductive coating have a plurality of overlapping pathway openings formed therethrough to isolate a respective shielding area of the conformal structure over desired circuit components or groups of circuit components. | 12-23-2010 |
20110316167 | ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME - An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads. | 12-29-2011 |
20120069523 | SYSTEM AND METHOD OF FORMING A PATTERNED CONFORMAL STRUCTURE - A system and method of forming a patterned conformal structure for an electrical system is disclosed. The conformal structure includes a dielectric coating shaped to conform to a surface of an electrical system, with the dielectric coating having a plurality of openings therein positioned over contact pads on the surface of the electrical system. The conformal structure also includes a patterned conductive coating layered on the dielectric coating and on the contact pads such that an electrical connection is formed between the patterned conductive coating and the contact pads. The patterned conductive coating comprises at least one of an interconnect system, a shielding structure, and a thermal path. | 03-22-2012 |
20130062630 | OVERLAY CIRCUIT STRUCTURE FOR INTERCONNECTING LIGHT EMITTING SEMICONDUCTORS - A system and method for packaging light emitting semiconductors (LESs) is disclosed. An LES device is provided that includes a heatsink and an array of LES chips mounted on the heatsink and electrically connected thereto, with each LES chip comprising connection pads and a light emitting area configured to emit light therefrom responsive to a received electrical power. The LES device also includes a flexible interconnect structure positioned on and electrically connected to each LES chip to provide for controlLES operation of the array of LES chips, with the flexible interconnect structure further including a flexible dielectric film configured to conform to a shape of the heatsink and a metal interconnect structure formed on the flexible dielectric film and that extends through vias formed in the flexible dielectric film so as to be electrically connected to the connection pads of the LES chips. | 03-14-2013 |
20140159213 | ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME - An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads. | 06-12-2014 |
20150108513 | OVERLAY CIRCUIT STRUCTURE FOR INTERCONNECTING LIGHT EMITTING SEMICONDUCTORS - A system and method for packaging light emitting semiconductors (LESs) is disclosed. An LES device is provided that includes a heatsink and an array of LES chips mounted on the heatsink and electrically connected thereto, with each LES chip comprising connection pads and a light emitting area configured to emit light therefrom responsive to a received electrical power. The LES device also includes a flexible interconnect structure positioned on and electrically connected to each LES chip to provide for controlLES operation of the array of LES chips, with the flexible interconnect structure further including a flexible dielectric film configured to conform to a shape of the heatsink and a metal interconnect structure formed on the flexible dielectric film and that extends through vias formed in the flexible dielectric film so as to be electrically connected to the connection pads of the LES chips. | 04-23-2015 |
Patent application number | Description | Published |
20130186626 | SUBTERRANEAN WELL INTERVENTIONLESS FLOW RESTRICTOR BYPASS SYSTEM - A method of variably restricting flow in a subterranean well can include resisting flow through a flow path, and then selectively opening a pressure barrier which previously prevented flow through another flow path. The flow paths are configured for parallel flow. A flow restrictor system for use with a subterranean well can include at least two flow paths configured for parallel flow, a flow restrictor which resists flow through one flow path, and a pressure barrier which prevents flow through another flow path. The pressure barrier is selectively openable to permit flow through the second flow path. | 07-25-2013 |
20130206393 | ECONOMICAL CONSTRUCTION OF WELL SCREENS - A well screen for use in a subterranean well can include a loose filter media, a sandstone, a square weave mesh material, a foam, and/or a nonmetal mesh material. A method of installing a well screen in a subterranean well can include dispersing a material in a filter media of the well screen, after the well screen has been installed in the well, thereby permitting a fluid to flow through the filter media. A method of constructing a well screen can include positioning a loose filter media in an annular space between a base pipe and a shroud, so that the filter media filters fluid which flows through a wall of the base pipe. | 08-15-2013 |
20130206406 | ECONOMICAL CONSTRUCTION OF WELL SCREENS - A well screen for use in a subterranean well can include a loose filter media, a sandstone, a square weave mesh material, a foam, and/or a nonmetal mesh material. A method of installing a well screen in a subterranean well can include dispersing a material in a filter media of the well screen, after the well screen has been installed in the well, thereby permitting a fluid to flow through the filter media. A method of constructing a well screen can include positioning a loose filter media in an annular space between a base pipe and a shroud, so that the filter media filters fluid which flows through a wall of the base pipe. | 08-15-2013 |
20150034301 | ECONOMICAL CONSTRUCTION OF WELL SCREENS - A well screen for use in a subterranean well can include a loose filter media, a sandstone, a square weave mesh material, a foam, and/or a nonmetal mesh material. A method of installing a well screen in a subterranean well can include dispersing a material in a filter media of the well screen, after the well screen has been installed in the well, thereby permitting a fluid to flow through the filter media. A method of constructing a well screen can include positioning a loose filter media in an annular space between a base pipe and a shroud, so that the filter media filters fluid which flows through a wall of the base pipe. | 02-05-2015 |
Patent application number | Description | Published |
20120037357 | Crimped End Wrapped on Pipe Well Screen - A well screen is constructed by positioning a crimp ring encircling and over an end of a wrapped-on-pipe screen layer on a tubular base pipe. The crimp ring is plastically deformed about an outer surface of the screen layer. A bead of weld is applied to affix the crimp ring to the base pipe. | 02-16-2012 |
20140014314 | Shunt Tube Connection Assembly and Method - A shunt tube assembly comprises a shunt tube and a jumper tube comprising a first end. The shunt tube comprises a non-round cross section, and the first end of the jumper tube is coupled to the shunt tube at a coupling. The first end of the jumper tube comprises a substantially round cross section at the coupling. | 01-16-2014 |
20140110131 | Gravel Packing Apparatus having a Jumper Tube Protection Assembly - A gravel packing assembly has first and second joints each including a sand control screen assembly having a filter medium positioned exteriorly of a base pipe and a slurry delivery subassembly positioned exteriorly of the sand control screen assembly. The slurry delivery subassembly includes at least one transport tube extending longitudinally along at least a portion of the sand control screen assembly. At least one jumper tube is coupled to and extends between the at least one transport tube of the first joint and the at least one transport tube of the second joint. A jumper tube protection assembly extends between the first and second joints and is positioned exteriorly about the at least one jumper tube. | 04-24-2014 |
20140110132 | Gravel Packing Apparatus having a Rotatable Slurry Delivery Subassembly - A gravel packing assembly has first and second joints each including a sand control screen assembly having a filter medium positioned exteriorly of a base pipe and a slurry delivery subassembly rotatably mounted exteriorly on the sand control screen assembly. The slurry delivery subassembly includes at least one transport tube extending longitudinally along at least a portion of the sand control screen assembly. At least one jumper tube is coupled to and extends between the at least one transport tube of the first joint and the at least one transport tube of the second joint. The at least one transport tube of the first joint is axially aligned with the at least one transport tube of the second joint by rotating the slurry delivery subassembly of the first joint relative to the sand control screen of the first joint after the two joints are coupled together. | 04-24-2014 |
20140116727 | WELL SCREEN WITH CHANNEL FOR SHUNT OR CABLE LINE - Disclosed herein is a downhole well screen, having a base pipe with a filter mounted thereon with the filter comprising plurality of spaced layers including a screen layer. A longitudinally extending channel is formed in the well screen by plastically deforming the filter. The channel is selected to be of a size and shape to accommodate well control lines. | 05-01-2014 |
20140158373 | Gravel Packing Apparatus Having Locking Jumper Tubes - A gravel packing apparatus has first and second joints each including a sand control screen assembly having a filter medium positioned exteriorly of a base pipe and a slurry delivery subassembly positioned exteriorly of the sand control screen assembly. Each slurry delivery subassembly includes a transport tube extending longitudinally along at least a portion of the sand control screen assembly. A jumper tube extends between and is sealably coupled to the transport tube of the first joint and the transport tube of the second joint. A first locking assembly is positioned between the jumper tube and the transport tube of the first joint and a second locking assembly is positioned between the jumper tube and the transport tube of the second joint. | 06-12-2014 |
20140262208 | Shunt Tube Connection and Distribution Assembly and Method - A shunt tube assembly comprises a plurality of shunt tubes, a jumper tube, and a coupling member configured to provide fluid communication between the jumper tube and the plurality of shunt tubes. The coupling member can comprise a first end and a second end. The coupling member may be configured to provide a sealing engagement between the coupling member and the jumper tube at the first end, and the coupling member may be configured to provide a sealing engagement between the coupling member and the plurality of jumper tubes at the second end. | 09-18-2014 |
20140299310 | Gravel Packing Apparatus having a Rotatable Slurry Delivery Subassembly - A gravel packing assembly has first and second joints each including a sand control screen assembly having a filter medium positioned exteriorly of a base pipe and a slurry delivery subassembly rotatably mounted exteriorly on the sand control screen assembly. The slurry delivery subassembly includes at least one transport tube extending longitudinally along at least a portion of the sand control screen assembly. At least one jumper tube is coupled to and extends between the at least one transport tube of the first joint and the at least one transport tube of the second joint. The at least one transport tube of the first joint is axially aligned with the at least one transport tube of the second joint by rotating the slurry delivery subassembly of the first joint relative to the sand control screen of the first joint after the two joints are coupled together. | 10-09-2014 |
20140332211 | Shunt Tube Connection Assembly and Method - A method of gravel packing comprises passing a slurry through a first shunt tube, passing the slurry through a coupling, and disposing the slurry about a well screen assembly below the coupling. The first shunt tube comprises a first cross-sectional shape along its length, and the coupling comprises a coupling between the first shunt tube and a jumper tube. The jumper tube comprises a substantially round cross-section at the coupling. | 11-13-2014 |
20150136391 | GRAVEL PACKING APPARATUS HAVING A JUMPER TUBE PROTECTION ASSEMBLY - A gravel packing apparatus is provided, including first and second joints, each including a sand control screen assembly including a base pipe and a filter medium positioned exteriorly of the base pipe; and a slurry delivery subassembly positioned exteriorly of the sand control screen assembly, the slurry delivery subassembly including a ring assembly positioned around the base pipe; and a transport tube extending through the ring assembly and longitudinally along the sand control screen assembly; a jumper tube coupled to, and extending between, the transport tube of the first joint and the transport tube of the second joint; and a cage assembly extending circumferentially about respective portions of the first and second joints and positioned exteriorly of the jumper tube, the cage assembly comprising a plurality of cage sections that are each independently connected to the respective ring assemblies of the first and second joints. A method is also provided. | 05-21-2015 |
Patent application number | Description | Published |
20080311107 | Novel Gene Disruptions, Compositions and Methods Relating Thereto - The present invention relates to transgenic animals, as well as compositions and methods relating to the characterization of gene function. Specifically, the present invention provides transgenic mice comprising disruptions in PRO188, PRO235, PRO266, PRO337, PRO361, PRO539, PRO698, PRO717, PRO846, PRO874, PRO98346, PRO1082, PRO1097, PRO1192, PRO1268, PRO1278, PRO1303, PRO1308, PRO1338, PRO1378, PRO1415, PRO1867, PRO1890, PRO3438, PRO19835, PRO36915, PRO36029, PRO4999, PRO5778, PRO5997, PRO6079, PRO6090, PRO7178, PRO21184, PRO7434, PRO9822, PRO9833, PRO9836, PRO9854, PRO9862, PRO10284, PRO37510, PRO35444, PRO20473, PRO21054 or PRO35246 genes. Such in vivo studies and characterizations may provide valuable identification and discovery of therapeutics and/or treatments useful in the prevention, amelioration or correction of diseases or dysfunctions associated with gene disruptions such as neurological disorders; cardiovascular, endothelial or angiogenic disorders; eye abnormalities; immunological disorders; oncological disorders; bone metabolic abnormalities or disorders; lipid metabolic disorders; or developmental abnormalities. | 12-18-2008 |
20100233153 | NOVEL GENE DISRUPTIONS, COMPOSITIONS AND THE METHODS RELATING THERETO - The present invention relates to transgenic animals, as well as compositions and methods relating to the characterization of gene function. Specifically, the present invention provides transgenic mice comprising disruptions in PRO1105, PRO1279 or PRO1783 genes. Such in vivo studies and characterizations may provide valuable identification and discovery of therapeutics and/or treatments useful in the prevention, amelioration or correction of diseases or dysfunctions associated with gene disruptions such as neurological disorders; cardiovascular, endothelial or angiogenic disorders; eye abnormalities; immunological disorders; oncological disorders; bone metabolic abnormalities or disorders; lipid metabolic disorders; or developmental abnormalities. | 09-16-2010 |
20110200579 | NOVEL GENE DISRUPTIONS, COMPOSITIONS AND METHODS RELATING THERETO - The present invention relates to transgenic animals, as well as compositions and methods relating to the characterization of gene function. Specifically, the present invention provides transgenic mice comprising disruptions in PRO57290 genes. Such in vivo studies and characterizations may provide valuable identification and discovery of therapeutics and/or treatments useful in the prevention, amelioration or correction of diseases or dysfunctions associated with gene disruptions such as cardiovascular, endothelial or angiogenic disorders; immunological disorders; oncological disorders; bone metabolic abnormalities or disorders; or developmental abnormalities. | 08-18-2011 |
20120005766 | Methods of identifying agents that modulate phenotypes related to disruptions, of a gene encoding PRO235 polypeptide - The present invention relates to transgenic animals, as well as compositions and methods relating to the characterization of gene function. Specifically, the present invention provides transgenic mice comprising disruptions in PRO188, PRO235, PRO266, PRO337, PRO361, PRO539, PRO698, PRO717, PRO846, PRO874, PRO98346, PRO1082, PRO1097, PRO1192, PRO1268, PRO1278, PRO1303, PRO1308, PRO1338, PRO1378, PRO1415, PRO1867, PRO1890, PRO3438, PRO19835, PRO36915, PRO36029, PRO4999, PRO5778, PRO5997, PRO6079, PRO6090, PRO7178, PRO21184, PRO7434, PRO9822, PRO9833, PRO9836, PRO9854, PRO9862, PRO10284, PRO37510, PRO35444, PRO20473, PRO21054 or PRO35246 genes. Such in vivo studies and characterizations may provide valuable identification and discovery of therapeutics and/or treatments useful in the prevention, amelioration or correction of diseases or dysfunctions associated with gene disruptions such as neurological disorders; cardiovascular, endothelial or angiogenic disorders; cyc abnormalities; immunological disorders; oncological disorders; bone metabolic abnormalities or disorders; lipid metabolic disorders; or developmental abnormalities. | 01-05-2012 |
Patent application number | Description | Published |
20100020818 | SHARING BUFFER SPACE IN LINK AGGREGATION CONFIGURATIONS - In link aggregation configurations, a data packet may be copied into a buffer space of a first NIC. Load balancing techniques may determine that the packet should be transmitted by a second NIC. The packet exists in memory that the second NIC cannot access. The data packet is copied into memory accessible to the second NIC or the memory location of the packet is registered with the NIC. A copy penalty is incurred if a packet is copied from a first buffer space to a second buffer space. A registration penalty is incurred if the location within the first buffer space is registered with the second NIC. Functionality can be implemented within a link aggregation configuration to register buffer space shared among interconnected NICs. Sharing of buffer space between interconnected NICs allows any one of the NICs to access data within the shared buffer space without incurring a penalty. | 01-28-2010 |
20100153974 | OBTAIN BUFFERS FOR AN INPUT/OUTPUT DRIVER - Disclosed is a computer implemented method, computer program product, and apparatus to obtain buffers in a multiprocessor system. A software component receives a call from an I/O device driver for a buffer, the call including at least one parameter, and walks a bucket data structure to a current bucket. The software component then determines whether the current bucket is free, and obtains a buffer list contained with the current bucket. Responsive to a determination that the current bucket is free, the software component determines whether sufficient buffers are obtained based on the parameter. Upon determining there are sufficient buffers obtained, the software component provides the current bucket and a second bucket as a single buffer list to the I/O device driver. | 06-17-2010 |
20100251268 | SERIALIZED ACCESS TO AN I/O ADAPTER THROUGH ATOMIC OPERATION - Disclosed is a computer implemented method, computer program product, and apparatus to enqueue one or more packets in a device driver for an I/O adapter. A device driver receives, by a processor executing the device driver, a reference to a list of transmit packets. The device driver may then atomically fetch and set a transmit active flag, wherein atomically setting comprises determining a former status of the transmit active flag. Responsive to a determination that a former status of the transmit active flag is different than a current status of the transmit active flag, the device driver atomically removes, by a processor executing the device driver, any packets referenced by a host machine transmit queue reference. The device driver pre-pends transmit packets referenced by the host machine transmit queue reference to the list of transmit packets to form an augmented list of transmit packets. The device driver builds a work request based on the augmented list of transmit packets. The device driver notifies the I/O adapter of the work request. The device driver atomically resets the transmit active flag. | 09-30-2010 |
20100296518 | Single DMA Transfers from Device Drivers to Network Adapters - Methods and arrangements of data communications are discussed. Embodiments include transformations, code, state machines or other logic to provide data communications. An embodiment may involve receiving from a protocol stack a request for a buffer to hold data. The data may consist of all or part of a payload of a packet. The embodiment may also involve allocating space in a buffer for the data and for a header of a packet. The protocol stack may store the data in a portion of the buffer and hand down the buffer to a network device driver. The embodiment may also involve the network device driver transferring the entire packet from the buffer to a communications adapter in a single direct memory access (DMA) operation. | 11-25-2010 |
20110096659 | Zero Packet Loss Energy Efficient Ethernet Link Transition Via Driver Fast Failover - A mechanism for zero packet loss with energy efficient Ethernet link transition via driver fast failover is provided. By default, the mechanism uses a primary adapter running at low speed with low energy usage and a secondary adapter that is disabled. This default configuration is used during periods of low link utilization. When system or input/output load is such that high speed is required, then the mechanism enables the secondary adapter to its highest supported link speed. All transmit traffic in progress running over the primary adapter will complete, and upon completion, the driver generates an address resolution request and sends the request over the secondary adapter. After this process completes, the primary adapter transitions to link down and zero packet loss transition completes. | 04-28-2011 |
20110103396 | SELECTIVE LINK AGGREGATION IN A VIRTUALIZED ENVIRONMENT - A method, system, and computer usable program product for selective link aggregation in a virtualized data processing environment are provided in the illustrative embodiments. A data packet is received at a switch. An identifier associated with the data packet is determined. The identifier corresponds to a logical partition in a logical partitioned data processing system. A lookup is performed in a data structure to determine a set of ports associated with the identifier. The set of ports is retrieved from the data structure. A port is selected from the set of ports and the data packet is transmitted from the port to the logical partition. | 05-05-2011 |
20110231406 | MULTICAST ADDRESS SEARCH INCLUDING MULTIPLE SEARCH MODES - An information handling system (IHS) includes a network adapter having a hardware address store that stores multicast addresses and a device driver that stores multicast addresses in a software address store. When there is no more storage space available in the hardware address store for multicast addresses, the device driver stores multicast addresses in the software address store. When the IHS receives a multicast information packet, the network adapter searches the hardware address store for a multicast address corresponding to that multicast information packet. If the search of the hardware address store does not find that multicast address, then the device driver searches the software address store for that multicast address. The IHS may prioritize the multicast addresses in the hardware address store and the software address store on a most frequently used basis, a most recently used basis or a most popular basis. For example, the hardware address store may store addresses that are more frequently used than those in the software address store. | 09-22-2011 |
20110264789 | DYNAMIC SETTING OF MBUF MAXIMUM LIMITS - A data processing system stack initializes a first mbuf chain limit to a pre-set level. It receives at least one packet. The system receives at least one packet. The system returns an mbuf data structure in response to receiving at least one packet from an IP address. The system measures a health of the network connection to determine whether the network connection satisfies a first health criterion. The system reduces the mbuf chain limit to a second mbuf chain limit, responsive to the health of the network connection not satisfying the first health criterion. The system measures the health of the network connection to determine whether the network connection meets a second health criterion. | 10-27-2011 |
20110265095 | Resource Affinity via Dynamic Reconfiguration for Multi-Queue Network Adapters - A mechanism is provided for providing resource affinity for multi-queue network adapters via dynamic reconfiguration. A device driver allocates an initial queue pair within a memory. The device driver determines whether workload of the data processing system has risen above a predetermined high threshold. Responsive to the workload rising above the predetermined high threshold, the device driver allocates and initializes an additional queue pair in the memory. The device driver programs a receive side scaling (RSS) mechanism in a network adapter to allow for dynamic insertion of an additional processing engine associated with the additional queue pair. The device driver enables transmit tuple hashing to the additional queue pair. | 10-27-2011 |
20110271008 | Selective TCP Large Receive Aggregation Based On IP Destination Address - An information handling device receives a packet and determines a packet destination for the packet. In turn, the information handling device either aggregates the packet in response to determining that the packet destination is a local destination, or forwards the packet in response to determining that the packet destination is a non-local destination. | 11-03-2011 |
20110321039 | VIRTUAL NETWORK PACKET TRANSFER SIZE MANAGER - The method determines whether a particular virtual adapter of a virtual network IHS may perform enhanced packet communication transfer of larger sizes than those of physical network IHSs. The method registers each virtual adapter maximum receive unit (MRU) value in an MRU attribute table within a hypervisor virtual switch. The hypervisor virtual switch provides communication pathways for packet transfers between virtual network IHS virtual adapters and also between physical adapters. The method determines if a sending virtual adapter is sending a packet to a receiving virtual adapter that is local or a remote virtual trunk adapter. The method determines if the receiving virtual adapter exhibits a registered MRU value. If the receiving virtual adapter exhibits a registered MRU value, the method provides for larger sizes of packet transfers for those particular packets. | 12-29-2011 |
20120124572 | VIRTUALIZATION OF VENDOR SPECIFIC NETWORK INTERFACES OF SELF-VIRTUALIZING INPUT/OUTPUT DEVICE VIRTUAL FUNCTIONS - A vendor independent partition interface between a logical partition and an adjunct partition associated with a self-virtualizing IO resource is used to effectively abstract away vender-specific interface details for the self-virtualizing IO resource. By doing so, vender-specific implementation details may be isolated from the operating systems resident in logical partitions, thus requiring only changes in vendor specific firmware in order to support new or revised self-virtualizing IO resources. | 05-17-2012 |
20120180047 | PRESERVING TRAFFIC CLASS PRIORITY QoS WITH SELF-VIRTUALIZING INPUT/OUTPUT DEVICE - Frame wrapping such as Q-in-Q frame wrapping is used to enforce QoS prioritization with a converged or multi-function self-virtualizing IO resource such as a converged SRIOV network adapter. Frame wrapping may be used to avoid conflicting priorities from frames associated with virtual functions for which ACLs are not enforced, and thereby preserve QoS prioritization for lossless traffic classes. | 07-12-2012 |
20120210039 | SELECTIVE LINK AGGREGATION IN A VIRTUALIZED ENVIRONMENT - A method for selective link aggregation in a virtualized data processing environment is provided in the illustrative embodiments. A data packet is received at a switch. An identifier associated with the data packet is determined. The identifier corresponds to a logical partition in a logical partitioned data processing system. A lookup is performed in a data structure to determine a set of ports associated with the identifier. The set of ports is retrieved from the data structure. A port is selected from the set of ports and the data packet is transmitted from the port to the logical partition. | 08-16-2012 |
20120210337 | Resource Affinity Via Dynamic Reconfiguration for Multi-Queue Network Adapters - A mechanism is provided for providing resource affinity for multi-queue network adapters via dynamic reconfiguration. A device driver allocates an initial queue pair within a memory. The device driver determines whether workload of the data processing system has risen above a predetermined high threshold. Responsive to the workload rising above the predetermined high threshold, the device driver allocates and initializes an additional queue pair in the memory. The device driver programs a receive side scaling (RSS) mechanism in a network adapter to allow for dynamic insertion of an additional processing engine associated with the additional queue pair. The device driver enables transmit tuple hashing to the additional queue pair. | 08-16-2012 |
20130204933 | MULTICAST MESSAGE FILTERING IN VIRTUAL ENVIRONMENTS - Various systems, processes, and products may be used to filter multicast messages in virtual environments. In particular implementations, a system, process, and product for filtering multicast messages in virtual environments may include the ability to determine whether a multicast message has been received, examine a local filtering store for a match for the destination address of the multicast message, and send the message to a number of virtual machines if a match for the address is found. The system, process, and product may also include the ability to analyze a filtering store of at least one of the virtual machines for a match for the address if a match is not found in the local filtering store and send the message to a number of the virtual machines if a match for the address is found in a filtering store of one of the virtual machines. | 08-08-2013 |
20130205296 | MULTICAST MESSAGE FILTERING IN VIRTUAL ENVIRONMENTS - Various systems, processes, and products may be used to filter multicast messages in virtual environments. In particular implementations, a system, process, and product for filtering multicast messages in virtual environments may include the ability to determine whether a multicast message has been received, examine a local filtering store for a match for the destination address of the multicast message, and send the message to a number of virtual machines if a match for the address is found. The system, process, and product may also include the ability to analyze a filtering store of at least one of the virtual machines for a match for the address if a match is not found in the local filtering store and send the message to a number of the virtual machines if a match for the address is found in a filtering store of one of the virtual machines. | 08-08-2013 |
20150085879 | Memory Transfer Optimization of Network Adapter Data Placement when Performing Header-Data Split Operations - Mechanisms are provided, in a data processing system comprising a host system and a network adapter, for processing received frames of data over a network connection. The mechanisms receive, in the host system from the network adapter, a plurality of frames of data. The mechanisms record, by the host system, for each frame in the plurality of frames, a header size associated with the frame over a current predetermined interval. The mechanisms determine, by the host system, a receive buffer address offset for receive buffers in the host system for a next predetermined interval based on the recorded header sizes of the plurality of frames over the current predetermined interval. In addition, the mechanisms configure, by the host system, the network adapter to utilize the receive buffer address offset to perform data transfers with the host system. | 03-26-2015 |
20150085880 | Memory Transfer Optimization of Network Adapter Data Placement when Performing Header-Data Split Operations - Mechanisms are provided, in a data processing system comprising a host system and a network adapter, for processing received frames of data over a network connection. The mechanisms receive, in the host system from the network adapter, a plurality of frames of data. The mechanisms record, by the host system, for each frame in the plurality of frames, a header size associated with the frame over a current predetermined interval. The mechanisms determine, by the host system, a receive buffer address offset for receive buffers in the host system for a next predetermined interval based on the recorded header sizes of the plurality of frames over the current predetermined interval. In addition, the mechanisms configure, by the host system, the network adapter to utilize the receive buffer address offset to perform data transfers with the host system. | 03-26-2015 |
20150095472 | Resource Affinity Via Dynamic Reconfiguration for Multi-Queue Network Adapters - A mechanism is provided for providing resource affinity for multi-queue network adapters via dynamic reconfiguration. A device driver allocates an initial queue pair within a memory. The device driver determines whether workload of the data processing system has risen above a predetermined high threshold. Responsive to the workload rising above the predetermined high threshold, the device driver allocates and initializes an additional queue pair in the memory. The device driver programs a receive side scaling (RSS) mechanism in a network adapter to allow for dynamic insertion of an additional processing engine associated with the additional queue pair. The device driver enables transmit tuple hashing to the additional queue pair. | 04-02-2015 |
Patent application number | Description | Published |
20090039942 | LEVEL SHIFTER - A level converter comprises first and second latches, and first through fourth transistors. The first latch has first and second power supply terminals, and first and second nodes. The second latch has third and fourth power supply terminals, and third and fourth nodes. The first transistor has a first current electrode coupled to the first node, a control electrode coupled to receive a first bias voltage, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to the third node, and a control electrode coupled to receive a second bias voltage. The third transistor has a first current electrode coupled to the second node, a control electrode coupled to receive the first bias voltage, and a second current electrode. The fourth transistor has a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to receive the second bias voltage, and a second current electrode coupled to the fourth node. | 02-12-2009 |
20090097285 | VARIABLE LOAD, VARIABLE OUTPUT CHARGE-BASED VOLTAGE MULTIPLIERS - A charge-based voltage multiplier device comprising a charge-pump circuit and a charge-pump controller is provided. The charge-pump circuit is configured to multiply an input voltage signal (V | 04-16-2009 |
20090243571 | Built-In Self-Calibration (BISC) Technique for Regulation Circuits Used in Non-Volatile Memory - A reference voltage regulation circuit ( | 10-01-2009 |
20110050326 | CHARGE PUMP WITH CHARGE FEEDBACK AND METHOD OF OPERATION - A charge pump charges a first capacitor to a predetermined input voltage using a first switch. The first switch is coupled to a first terminal of the first capacitor for coupling the first terminal to an input terminal that receives the predetermined input voltage. A second switch couples a second terminal of the first capacitor to a reference voltage terminal. Charge is sequentially transferred from the first capacitor to an output capacitance by using the first switch. A portion of charge is sequentially removed from the output capacitance to the input terminal using a third switch and a second capacitor. Configuration logic provides control signals to make one or more of a plurality of charge transfer capacitors switch the same as said first capacitor switches. | 03-03-2011 |
20110115549 | CHARGE PUMP FOR USE WITH A SYNCHRONOUS LOAD - A charge pump has circuitry and implements a method for monitoring a synchronous load by using a first voltage threshold below a target output voltage and a second voltage threshold above a target output voltage. An output terminal is coupled to the load. Charge is demanded by clocking the load. When the target output voltage passes below the first voltage threshold, a first value representing a present size of a charging capacitance is stored as a stored first value, and a second stored value representing a needed changed size of the charging capacitance is used. The present size of the charging capacitance is changed in response to the passing of the target output voltage below the first voltage threshold. When demand for charge from the load is reduced, a present value is saved and a prior value is restored to change the size of the charging capacitance. | 05-19-2011 |
20110133819 | LOW POWER CHARGE PUMP AND METHOD OF OPERATION - A charge pump and method for starting up a charge pump are provided. The charge pump comprises a plurality of charge pump cells and a start-up control circuit. Each charge pump cell has a clock terminal for receiving a delayed clock signal, an input terminal for receiving an input voltage, and an output terminal for providing a boosted voltage in response to receiving the clock signal and the input voltage. The start-up control circuit is coupled to the clock terminals of each of the plurality of charge pump cells. The start-up control circuit is for delaying the delayed clock signal provided to each charge pump cell of the plurality of charge pump cells. Each of the charge pump cells receives the delayed clock signal having a different predetermined delay so that each of the plurality of charge pump cells are enabled in a predetermined sequence during start-up of the charge pump. | 06-09-2011 |
20110221511 | VARIABLE INPUT VOLTAGE CHARGE PUMP - A device for providing a constant output voltage based on a variable input voltage is provided. The device may include: (1) a charge-pump comprising a plurality of cells, wherein each of the plurality of cells can be configured as an input cell, a stepping cell, or a load cell; (2) a comparator; and (3) a differentiator coupled to the comparator output, wherein the differentiator is configured to monitor the comparator output and produce a reset pulse each time the comparator output changes its state. The device may further include: (1) a decimator; (2) an up/down counter; and (3) a controller for detecting whether the device is operating in a first predetermined mode or a second predetermined mode, wherein the two modes relate to the configuration of the plurality of cells into the input cell, the stepping cell, and/or the load cell. | 09-15-2011 |
20110316592 | REFRESH OPERATION DURING LOW POWER MODE CONFIGURATION - A target circuit of an electronic device is placed in a suspended mode by disconnecting the target circuit from one or more voltage sources. A refresh controller periodically initiates a refresh operation during the suspended mode by temporarily reconnecting the target circuit to the one or more voltage sources for a duration sufficient to recharge capacitances of the target circuit. The refresh controller terminates the refresh operation by disconnecting the target circuit from the one or more voltage sources, thereby continuing the suspended mode of the electronic device. The refresh controller can employ a Very Low Frequency Oscillator (VLFO) to time the frequency of refresh operations. The VLFO manages the refresh initialization timing based on the voltage across a capacitor that is selectively charged or discharged so as to implement the refresh operation. The refresh controller further can employ a counter to time the duration of the refresh operation. | 12-29-2011 |
20120169404 | Exponential Charge Pump - An exponential multistage charge pump is disclosed. Node voltages in a pumpcell in one stage of the charge pump are used to control operation of clock drivers in a subsequent stage of the charge pump, thereby eliminating the need for level shifters. | 07-05-2012 |
20120176844 | READ CONDITIONS FOR A NON-VOLATILE MEMORY (NVM) - A method and memory are provided for determining a read reference level for a plurality of non-volatile memory cells. The method includes: performing a program operation of the plurality of non-volatile memory cells; determining a program level of a least programmed memory cell of the plurality of memory cells; performing an erase operation of the plurality of non-volatile memory cells; determining an erase level of a least erased memory cell of the plurality of memory cells; determining an operating window between the program level and the erase level; and setting the read reference level to be a predetermined offset from the erase level if the operating window is determined to compare favorably to a predetermined value. The memory includes registers for storing the program level and the erase level. | 07-12-2012 |
20130265828 | SMART CHARGE PUMP CONFIGURATION FOR NON-VOLATILE MEMORIES - A semiconductor memory device includes a non-volatile memory, a memory controller, and a charge pump system. The memory controller establishes first parameters for a first programming cycle of a first plurality of memory cells of the non-volatile memory prior to the first programming cycle being performed. The charge pump system includes a plurality of charge pumps and provides a first programming pulse for use in performing the first program cycle. The first programming pulse is provided by selecting, according to the first parameters, which of the plurality of charge pumps are to be enabled during the first program cycle and which are to be disabled during the first program cycle. | 10-10-2013 |
20130268717 | EMULATED ELECTRICALLY ERASABLE MEMORY HAVING SECTOR MANAGEMENT - A semiconductor memory device comprises a volatile memory and a non-volatile memory including a plurality of sectors. Each of the plurality of sectors configured to store a sector status indicator and a plurality of data records. A control module is coupled to the non-volatile memory and the volatile memory. The control module manages the sectors by scanning the sectors to identify the records with invalid data; changing the status indicator of a particular sector when all of the records in the particular sector are invalid, and discontinuing scanning the particular sector while all of the records in the particular sector are invalid. | 10-10-2013 |
20130290603 | EMULATED ELECTRICALLY ERASABLE MEMORY PARALLEL RECORD MANAGEMENT - A method of transferring data from a non-volatile memory (NVM) having a plurality of blocks of an emulated electrically erasable (EEE) memory to a random access memory (RAM) of the EEE includes accessing a plurality of records, a record from each block. A determination is made if any of the data signals of the first data signals are valid and thereby considered valid data signals. If there is only one or none that are valid, the valid data, if any is loaded into RAM and the process continues with subsequent simultaneous accesses. If more than one is valid, then the processes is halted until the RAM is loaded with the valid data, then the method continues with subsequent simultaneous accesses of records. | 10-31-2013 |
20140022005 | CONFIGURABLE MULTISTAGE CHARGE PUMP USING A SUPPLY DETECT SCHEME - A configurable multistage charge pump including multiple pumpcells, at least one bypass switch and control logic. The pumpcells are coupled together in series including a first pumpcell receiving an input voltage and at least one remaining pumpcell including a last pumpcell which generates an output voltage. Each bypass switch is coupled to selectively provide the input voltage to a pumpcell input of a corresponding one of the remaining pumpcells. The control logic is configured to determine one of multiple voltage ranges of the input voltage, to enable each pumpcell for a first voltage range and to disable and bypass at least one pumpcell for at least one other voltage range. A method of operating a multistage charge pump including detecting an input voltage, selecting a voltage range based on an input voltage, and enabling a number of cascaded pumpcells corresponding to the selected voltage range. | 01-23-2014 |
20140059398 | ADAPTIVE ERROR CORRECTION FOR NON-VOLATILE MEMORIES - Methods and systems are disclosed for adaptive error correction for non-volatile memories that dynamically adjust sense amplifier read detection windows. Memory control circuitry uses error correction code (ECC) routines to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry then dynamically adjusts sense amplifier read detection windows to allow for correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously suffered bit failures. The disclosed methods and systems can also be used with respect to memories that are not non-volatile memories. | 02-27-2014 |
20140078828 | NVM WITH CHARGE PUMP AND METHOD THEREFOR - A non-volatile memory device comprises an array of memory cells and a charge pump coupled to the memory cells. The charge pump is dynamically reconfigurable to operate in a bypass mode to provide a first voltage to the memory cells, a program mode to provide the first voltage to the memory cells, and an erase mode to provide a second voltage that has inverse polarity of the first voltage. | 03-20-2014 |
20140082257 | SYSTEMS AND METHODS FOR CODE PROTECTION IN NON-VOLATILE MEMORY SYSTEMS - Methods and systems are disclosed for code protection in non-volatile memory (NVM) systems. Information stored within NVM memory sectors, such as boot code or other code blocks, is protected using lockout codes and lockout keys written in program-once memory areas within the NVM systems. Further, lockout codes can be combined into a merged lockout code that can be stored in a merged protection register. The merged protection register is used to control write access to protected memory sectors. Lockout code/key pairs are written to the program-once area when a memory sector is protected. The program-once area, which stores the lockout code/key pairs, is not readable by external users. Once protected, a memory sector can not be updated without the lockout code/key pair. | 03-20-2014 |
20140244895 | Robust Sector ID Scheme for Tracking Dead Sectors to Automate Search and Copydown - A brownout tolerant EEPROM emulator ( | 08-28-2014 |
20140258792 | Symmetrical Data Replication For Failure Management In Non-Volatile Memory Systems - Methods and systems are disclosed for symmetrical replication of data within multiple data subsystems for failure management in non-volatile memory (NVM) systems. Disclosed embodiments perform symmetrical write operations to multiple different data block subsystems so that duplicate subsystems are created. As the subsystems are operated symmetrically, address locations and pointers are the same for each subsystem. If an error is detected in data within one subsystem, the duplicated data at the same symmetrical location within a duplicate subsystem can be used. As such, the endurance and lifetime of NVM systems is greatly enhanced. These extended lifetime NVM systems can then be used, for example, to emulate EEPROM (erasable programmable read only memory) systems. | 09-11-2014 |
20140266366 | COMPENSATED HYSTERESIS CIRCUIT - A compensated hysteresis circuit comprises a hysteresis circuit including an output node and a first control transistor. The first control transistor provides feedback to the hysteresis circuit. A temperature and voltage compensation circuit includes a self-biasing threshold control circuit including an input coupled to the output node of the hysteresis circuit, and a first trim transistor coupled between the first control transistor of the hysteresis circuit and the self-biasing threshold control circuit. | 09-18-2014 |
20140354364 | OSCILLATOR WITH STARTUP CIRCUITRY - An oscillator that includes a first source current leg and first sink current leg to source current and sink current, respectively, during a startup mode of oscillator operation. The oscillator includes a second source current leg and a second sink current leg to source current and sink current, respectively, during a second mode of oscillator operation. | 12-04-2014 |
20150103602 | SECTOR-BASED REGULATION OF PROGRAM VOLTAGES FOR NON-VOLATILE MEMORY (NVM) SYSTEMS - Methods and systems are disclosed for sector-based regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments regulate program voltages for NVM cells based upon feedback signals generated from sector return voltages that are associated with program voltage drivers that are driving program voltages to NVM cells within selected sectors an NVM array. As such, drops in program voltage levels due to IR (current-resistance) voltage losses in program voltage distribution lines are effectively addressed. This sector-based regulation of the program voltage effectively maintains the desired program voltage at the cells being programmed regardless of the sector being accessed for programming and the number of cells being programmed. Sector return voltages can also be used along with local program voltages to provide two-step feedback regulation for the voltage generation circuitry. Test mode configurations can also be provided using test input and/or output pads. | 04-16-2015 |
20150186049 | SYSTEM AND METHOD FOR LOW COST PATCHING OF HIGH VOLTAGE OPERATION MEMORY SPACE - A low semiconductor area impact mechanism for patching operations stored in a boot memory area is provided, thereby providing flexibility to such code. In this manner, current flash memory manager SCRAM, which is used for memory operations when the flash memory is unavailable (e.g., high voltage operations) can be replaced with a significantly smaller register area (e.g., a flip flop array) that provides a small patch space, variable storage, and stack. Embodiments provide such space saving without modification to the CPU core, but instead focus on the external flash memory manager. Patch code can be copied into a designated register space. Since such code used during flash memory inaccessibility is typically small, patching can be provided for just a small area of the possible flash memory map, and program flow can be controlled by presenting the CPU core's own address to redirect the program counter to the patch area. | 07-02-2015 |
20150235704 | Digital Control For Regulation Of Program Voltages For Non-Volatile Memory (NVM) Systems - Methods and systems are disclosed for digital control for regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments dynamically adjust program voltages based upon parameters associated with the cells to be programmed in order to account for IR (current-resistance) voltage drops that occur within program voltage distribution lines. Other voltage variations can also be accounted for with these dynamic adjustments, as well. The parameters for cells to be programmed can include, for example, cell address locations for the cells to be programmed, the number of cells to be programmed, and/or other desired parameters associated with the cells to be programmed. The disclosed embodiments use digital control values obtained from lookup tables based upon the cell parameters to adjust output voltages generated by voltage generation circuit blocks used to program the selected cells thereby tuning the program output voltage level to a predetermined desired level. | 08-20-2015 |