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Cumming, GB
David Cumming, Livingston GB
| Patent application number | Description | Published |
|---|---|---|
| 20100091112 | OBJECT POSITION AND ORIENTATION DETECTION SYSTEM - An object position and orientation detection system and in particular one which is capable of describing observed movement in 3 dimensions. In one example, a spherical patterned marker with concentric rings is imaged using one or more digital cameras, and the resulting images are processed to determine the position and orientation of an object to which the patterned marker is attached. The method of optical tracking employed by the system allows motion to be determined in six degrees of freedom. In conjunction with a suitable display, such as a projector, an interactive white board or similar application can be realised. | 04-15-2010 |
David Robert Sime Cumming, Glasgow GB
| Patent application number | Description | Published |
|---|---|---|
| 20090030293 | SENSING DEVICE, APPARATUS AND SYSTEM, AND METHOD FOR OPERATING THE SAME - A sensing device, apparatus and system, and method for operating the same are provided. The sensing apparatus includes a first module and a second module. The first module includes a controller, a transmitter and an array of sensor elements. The controller is capable of activating one or more sensor elements in the array independently of others in the array, in order to obtain a sensor output from the array at different times by using different sensor elements in said array. The transmitter is configured to transmit sensor data derived from the sensor output from the first module to a receiver of the second module. Each sensor element is a biological sensor for detecting the presence of the same analyte in the environment in which the sensor array is to be deployed. | 01-29-2009 |
| 20090206319 | SEMICONDUCTOR DEVICE FOR GENERATING AN OSCILLATING VOLTAGE - A semiconductor device which displays an oscillating voltage due to the creation of charge domains which includes a plurality of semiconductor layers and at least two electrodes spaced from one another in the direction of the layers, an upper of which has a composition and/or dimensions predetermined so that a charge therein balances a depletion from a surface charge of the upper layer on application of a potential difference across said electrodes. The electrodes may be in contact solely with the upper layer. A method of manufacturing the device is also provided. | 08-20-2009 |
Graham Robert Cumming, Cleveland GB
| Patent application number | Description | Published |
|---|---|---|
| 20110166382 | PROCESSES FOR OBTAINING A PHOSPHONIC ACID FROM A PHOSPHONIC ACID ANHYDRIDE - The present invention relates to a process for recovering a phosphonic acid. The present invention also relates to the conversion of a phosphonic acid to a phosphonic acid anhydride. | 07-07-2011 |
Iain William Cumming, Leicestershire GB
| Patent application number | Description | Published |
|---|---|---|
| 20090211991 | Filtering a dispersed phase (e.g. oil) from a continuous liquid (e.g. water) of a dispersion - Filtering a dispersed phase (e.g. oil) from a continuous liquid (e.g. water) of a dispersion a filter, for filtering a dispersed phase from a continuous liquid of a dispersion, the filter including a substrate having a plurality of apertures each extending directly through the substrate between a first surface and a second surface and a layer of material applied over at least a portion of the first surface, wherein the material rejects the continuous liquid to a greater extent than the dispersed liquid. | 08-27-2009 |
John Cumming, Macclesfield GB
| Patent application number | Description | Published |
|---|---|---|
| 20100152197 | (4-TERT-BUTYLPIPERAZIN-2-YL)(PIPERAZIN-1-YL)METHANONE-N-CARBOXAMIDE DERIVATIVES - The present invention relates to compounds of formula (I) | 06-17-2010 |
John Cumming, Cheshire GB
| Patent application number | Description | Published |
|---|---|---|
| 20090143449 | Bi-Aryl or Aryl-Heteroaryl Substituted Indoles - The present invention relates to substituted indoles of Formula (I) useful as pharmaceutical compounds for treating respiratory disorders. | 06-04-2009 |
John Graham Cumming, Macclesfield GB
| Patent application number | Description | Published |
|---|---|---|
| 20120004243 | AMIDE DERIVATIVES BEARING A CYCLOPROPYLAMINOACARBONYL SUBSTITUENT USEFUL AS CYTOKINE INHIBITORS - The invention concerns a compound of the Formula (I), wherein Qa is heteroaryl and is substituted with halogeno; R1 and R2 are hydrogen; and Qb is phenyl or heteroaryl, and Qb may optionally bear 1 or 2 substituents selected from hydroxy, halogeno and (1-6C)alkyl, or a pharmaceutically-acceptable salt thereof; processes for their preparation, pharmaceutical compositions containing them and their use in the treatment of diseases or medical conditions mediated by cytokines. | 01-05-2012 |
Kenneth Iain Cumming, Essex GB
| Patent application number | Description | Published |
|---|---|---|
| 20110300210 | CONTROLLED RELEASE NANOPARTICULATE CLOZAPINE COMPOSITIONS - Described are controlled release nanoparticulate formulations comprising a nanoparticulate agent to be administered and a rate-controlling polymer which functions to prolong the release of the agent following administration. The novel compositions release the agent following administration for a time period ranging from about 2 to about 24 hours or longer. | 12-08-2011 |
Mike Cumming, Kirkbymoorside GB
| Patent application number | Description | Published |
|---|---|---|
| 20110005765 | Sampling Skid for Subsea Wells - A system for sampling production well production fluids from a manifold interface panel on a subsea production manifold. In some embodiments, the system includes a remotely operated vehicle, a skid coupled to the remotely operated vehicle, a sample tank supported on the skid, and a fluid transfer pump operable to convey production fluid from at least one of the production wells through the manifold interface panel into the sample tank. | 01-13-2011 |
Pete Cumming, Wickwar GB
| Patent application number | Description | Published |
|---|---|---|
| 20090153194 | CLOCK CIRCUITRY - A circuit comprising: clock circuitry for supplying a first faster clock signal to a first circuit portion and a second slower clock signal to a second circuit portion, and varying the relative frequency of the first and second clock signals. Synchronisation logic generates pulses which indicate when to transfer data between the first and second circuit portions. The clock circuitry generates a first control signal at a predetermined time in each cycle of the first clock signal prior to a predetermined edge, and a second control signal at a predetermined time in each cycle of the second clock signal prior to a predetermined edge. A change in the relative frequency is conditional on a coincidence of the first and second control signals. The synchronisation generates the pulses such that there is at least one cycle of the first clock signal between those pulses, and such that there is only one of those pulses per cycle of the second clock signal. | 06-18-2009 |
Peter Cumming, Wotton-Under-Egde GB
| Patent application number | Description | Published |
|---|---|---|
| 20120023352 | ACTIVE POWER MANAGEMENT - A method of controlling the clock frequency of a processor executing software in a plurality of active periods, the method comprising, for each period: supplying to a power management application at least one parameter defining an execution profile for the period having high frequency and low frequency operating intervals; the power management application determining, based on said profile, granted clock frequencies for the high and low frequency operating intervals; the processor supplying to the power management application at the commencement of a period an operating cycle requirement for the period; the power management application determining, for each period, based on the operating cycle requirement, the length of the low frequency interval; and controlling the clock frequency in each interval based on the granted clock frequencies determined by the power management application. | 01-26-2012 |
Peter Cumming, Wotton-Under-Edge GB
| Patent application number | Description | Published |
|---|---|---|
| 20090287859 | DMA Engine - A circuit and corresponding method for transferring data. The circuit comprises: a CPU; a plurality of addressable devices; and a DMA engine coupled to the CPU and to those devices, the DMA engine comprising a plurality of DMA contexts each having fetch circuitry for fetching a DMA descriptor indicated by the CPU and transfer circuitry for transferring data from one to another of the devices based on a fetched descriptor. The DMA engine further comprises switching means operable to control a group of the contexts to alternate in a complementary sequence between fetching and performing a transfer, such that alternately one or more contexts in the group fetch whilst one or more others perform a transfer. | 11-19-2009 |
| 20110191507 | DMA ENGINE - A circuit comprising: an execution unit; a plurality of addressable devices; and a data transfer engine coupled to the execution unit and to the devices, operable to fetch a plurality of descriptors under control of the execution unit, and based on each of the fetched descriptors to perform a transfer of data from a respective first to a respective second of the devices. The DMA engine comprises delay circuitry operable to block, during a delay period running from an earlier of the transfers, any later of the transfers involving at least one of the same devices as the earlier transfer, the delay circuitry being arranged to control the blocking in dependence on an indication received in one of the descriptors. | 08-04-2011 |
Peter Cumming, Gloucestershire GB
| Patent application number | Description | Published |
|---|---|---|
| 20090273378 | CLOCK CONFIGURATION - A circuit and method for determining the frequency of a first oscillating reference signal generated by a first reference oscillator. The circuit comprises: a second reference oscillator arranged to generate a second oscillating reference signal having a known frequency, a boot memory storing boot code comprising clock configuration code, and a processor coupled to the boot memory and the second reference oscillator. The processor is arranged to execute the boot code from the boot memory upon booting, wherein when executed the clock configuration code operates the processor to determine the frequency of the first reference signal by reference to the second reference signal. | 11-05-2009 |
Peter Cumming, Wickwar GB
| Patent application number | Description | Published |
|---|---|---|
| 20090172380 | BOOTING AN INTEGRATED CIRCUIT - An integrated circuit comprising: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties. | 07-02-2009 |
| 20090172383 | BOOTING AN INTEGRATED CIRCUIT - An integrated circuit comprising: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties. | 07-02-2009 |
| 20120005471 | BOOTING AN INTEGRATED CIRCUIT - An integrated circuit is disclosed herein. In one embodiment, the integrated circuit includes: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties. | 01-05-2012 |