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Cremonesi
Carlo Cremonesi, Vaprio D'Adda IT
| Patent application number | Description | Published |
|---|---|---|
| 20080206945 | PROCESS FOR FORMING DIFFERENTIAL SPACES IN ELECTRONICS DEVICE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE - A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the whole electronic device; forming a first mask to cover the first transistor; removing the first conformal insulating layer not covered by the first mask; removing the first mask; forming a second conformal insulating layer of a second thickness on the whole device; and removing the insulating layers until the protective layer is exposed to form first spacers of a first width on the side walls of the gate electrodes of the first transistor and second spacers of a second width on the side walls of the gate electrodes of the second transistor. | 08-28-2008 |
| 20100047980 | PROCESS FOR FORMING DIFFERENTIAL SPACES IN ELECTRONICS DEVICE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE - A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the whole electronic device; forming a first mask to cover the first transistor; removing the first conformal insulating layer not covered by the first mask; removing the first mask; forming a second conformal insulating layer of a second thickness on the whole device; and removing the insulating layers until the protective layer is exposed to form first spacers of a first width on the side walls of the gate electrodes of the first transistor and second spacers of a second width on the side walls of the gate electrodes of the second transistor. | 02-25-2010 |
| 20100279486 | NONVOLATILE MEMORY HAVING CONDUCTIVE FILM BETWEEN ADJACENT MEMORY CELLS - A floating gate MOS transistor having a conductive floating gate electrode insulated from a semiconductor material having a main surface by a gate dielectric layer. At least one isolation region formed lateral to the gate electrode. An evacuation is formed in the isolation region and beneath the main surface of the semiconductor material layer. A conductive material fills the evacuation. A conductive control gate electrode is formed above the floating gate electrode. The floating gate electrode is laterally aligned to at least one isolation region. | 11-04-2010 |
Giovanni Cremonesi, Fiorenzuola D'Arda IT
| Patent application number | Description | Published |
|---|---|---|
| 20100156519 | ELECTRICAL SYSTEM, VOLTAGE REFERENCE GENERATION CIRCUIT, AND CALIBRATION METHOD OF THE CIRCUIT - A voltage generation circuit that includes: a voltage generator integrated in a semiconductor chip and structured to generate an output voltage in accordance with a calibration parameter; a heater operable to heat the voltage generator; a control device configured to receive the output voltage, activate the heater and provide the calibration parameter to the voltage generator. | 06-24-2010 |
Giovanni Cremonesi, Fiorenzuola D'Arda (piacenza) IT
| Patent application number | Description | Published |
|---|---|---|
| 20110156789 | CONTROL SYSTEM FOR A PHASE GENERATOR AND CORRESPONDING CONTROL METHOD - A control system for a phase generator including a delay block including delay units, and first and second multiplexers configured to receive output signals of each of the delay units and to respectively supply first and second output signals. The control system may include a controller configured to drive the first multiplexer and the second multiplexer respectively with a first select signal and a second select signal, a detection module configured to detect a phase difference between the first output signal and the second output signal and to generate a corresponding digital phase shift signal, the detection module including a phase comparator, and a Time-Digital converter circuit coupled thereto and having logic elements configured to generate the digital phase shift signal, and a logic circuit connected to the detection module and configured to process the digital phase shift signal and to generate a signal indicative of a control executed. | 06-30-2011 |
Susanna Cremonesi, Verona IT
| Patent application number | Description | Published |
|---|---|---|
| 20100240661 | AZABICYCLO [3. 1. 0] HEXYL DERIVATIVES AS MODULATORS OF DOPAMINE D3 RECEPTORS - The present invention relates to novel compounds of formula (I) or a salt thereof: | 09-23-2010 |