Patent application number | Description | Published |
20130016576 | TIME DIVISION MULTIPLEXING SENSE AMPLIFIERAANM O'CONNELL; Cormac MichaelAACI KanataAACO CAAAGP O'CONNELL; Cormac Michael Kanata CA - A circuit comprises a plurality of memory cells, a word line, a plurality of pairs of bit lines, a pre-charge and equalization device, a column select device, and a sense amplifier. The word line is configured to control the plurality of memory cells. Each pair of bit lines of the plurality of pairs of bit lines corresponds to a memory cell of the plurality of memory cells and is coupled to a pair of switches. The sense amplifier is coupled to the plurality of pairs of bit lines, the pre-charge and equalization device, and the column select device. | 01-17-2013 |
20130212449 | SELF-REPAIRING MEMORY - A memory array has a plurality of rows including a plurality of memory words. Each first bit of a plurality of first bits is associated with a memory word of the each row. A state of the each first bit indicates whether the associated memory word has had an error. Each redundancy row of a plurality of redundancy rows includes a plurality of redundancy words. Each redundancy word is associated with a memory word. A corrected data cache has at least one repair word configured to store corrected data and at least one status bit associated with the at least one repair word, the status bit indicating whether the corrected data stored in the repair word is a pending repair. The corrected data cache is configured to write the corrected data stored in the repair word to at least one of a counterpart memory word or a counterpart redundancy word. | 08-15-2013 |
20130215695 | SELF-REPAIRING MEMORY - A memory array has a plurality of rows. Each row of the plurality of rows includes a plurality of memory words. Each first bit of a plurality of first bits is associated with a memory word of the each row. A state of the each first bit indicates whether the memory word associated the each first bit has had an error. Each redundancy row of a plurality of redundancy rows includes a plurality of redundancy words. Each redundancy word is associated with a memory word. Each second bit of a plurality of second bits is associated with a redundancy word of the plurality of redundancy words of the each row of the plurality of redundancy rows. A state of the each second bit indicates whether the redundancy word associated with the each second bit has had an error. | 08-22-2013 |
20140078844 | MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR ACCESSING THE MEMORY CIRCUITS - A sense amplifier includes a first transistor. The first transistor includes a gate connected to a bit line, and a first source/drain (S/D) electrically coupled with a global bit line. The sense amplifier further includes a second transistor. The second transistor includes a gate connected to a first signal line, and a first S/D coupled to the global bit line, wherein the second transistor is configured to pre-charge the bit line. | 03-20-2014 |
20140119135 | MEMORY ARCHITECTURE - A first current value flowing through a transistor coupled with a storage node of a memory cell is determined when the transistor is off. A second current value flowing through the transistor is determined when the transistor is in on. A first reference voltage value at a reference node of the memory cell when the transistor is off is higher than a second reference voltage value at the reference node when the transistor is on. Based on the first current value, the second current value, and a relationship between the first current value and the second current value, a number of memory cells to be coupled with a data line associated with the memory cell is determined. | 05-01-2014 |
20140241086 | MEMORY STRUCTURE - A memory structure includes a memory row of a memory array, a plurality of first bits, a first redundancy row, and a plurality of second bits. The memory row includes a plurality of memory words. The plurality of first bits is configured to indicate whether an individual memory word of the plurality of memory words of the memory row has an error. The first redundancy row includes a plurality of first redundancy words. The plurality of second bits is configured to indicate whether an individual first redundancy word of the plurality of first redundancy words of the first redundancy row has an error. | 08-28-2014 |
20140241087 | SENSE AMPLIFIER - A sense amplifier comprises a cross coupled pair of inverters, a first transistor, a second transistor, and a capacitive device. The cross coupled pair of inverters includes a first end, a second end, and a third end. The first end is configured to receive a first supply voltage. The second end is coupled with a first terminal of the capacitive device and a first terminal of the first transistor. The third end is coupled with a second terminal of the capacitive device and a first terminal of the second transistor. A second terminal of the first transistor and a second terminal of the second transistor are coupled together and are configured to receive a first control signal. A third terminal of the first transistor and a third terminal of the second transistor are coupled together and are configured to receive a second supply voltage different from the first supply voltage. | 08-28-2014 |
20140282332 | FAULT INJECTION OF FINFET DEVICES - Defect-describing (or “cut”) layer(s) for describing defects associated with different sides of a 3-dimensional (3D) structure enable fault modeling to determine the effect of position and location of defects on transistor performance. One or more defect-describing layers are used to identify the coordinates and sides of the 3D structures of the defects. The defect-describing layer(s) enables fault-modeling for 3D structures to understand the effects of faults on different locations, especially for defects associated with the fins of the finFET devices. Faults are injected to different locations and sides of fins and are modeled with different test vectors, test parameters and testing devices to identify detectable faults. The fault modeling would help identify the sources of defects and also improve layout design of finFET device structures. | 09-18-2014 |