Cooray
Boyd Cooray, Southampton GB
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20120126164 | Thermal Insulation System for Buildings and for Liquid Storage and Transportation - Insulating compositions in the form of aqueous dispersions which comprise hollow borosilicate glass spheres or ceramic microspheres, wax encapsulated thermoset particles and spherical thermoplastic microspheres and an emulsion polymer or redispersible powder binder. The compositions may applied as a primer or top coat in interior and/or exterior of new and existing buildings or for the insulation of pipes, cylinders and tanks containing and transporting hot or cold liquids or low boiling point liquids. | 05-24-2012 |
Florence Nawalage Cooray, Kelaniya LK
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20150231606 | PHOTOCATALYST, AND METHOD FOR PRODUCING PHOTOCATALYST - A photocatalyst, represented by the following general formula (1): | 08-20-2015 |
Nawalage Florence Cooray, Kawasaki JP
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20110070525 | ELECTROLYTE COMPOSITION, SOLID ELECTROLYTE MEMBRANE, SOLID POLYMER FUEL CELL AND MANUFACTURING METHOD FOR SOLID ELECTROLYTE MEMBRANE - An electrolyte composition that shows low methanol cross-over and exhibits high proton conductivity when used as a solid electrolyte for solid polymer fuel cells or the like, and a solid electrolyte membrane and a solid polymer fuel cell that use the electrolyte composition are provided. This electrolyte composition comprises a perfluorocyclobutane-containing polymer having a specific structure. High proton conductivity is provided by sulfonic acid groups connected to the benzene rings. Reduction of methanol crossover is realized by introduction of a rigid structure with aromatic rings, or a combination o a rigid structure with aromatic rings and a three-dimensional cross-linked structure. | 03-24-2011 |
Nirajan L. Cooray, Folsom, CA US
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20140189659 | HANDLING OF BINARY TRANSLATED SELF MODIFYING CODE AND CROSS MODIFYING CODE - A processor core includes a processor to execute a first translated instruction translated from a first instruction stored in first page of a memory. The processor also includes a translation indicator agent (XTBA) to store a first translation indicator that is read from a physical map (PhysMap) in the memory. In an embodiment, the first translation indicator is to indicate whether the first page has been modified after the first instruction is translated. Other embodiments are described as claimed. | 07-03-2014 |
Niranjan Cooray, Folsom, CA US
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20140189250 | Store Forwarding for Data Caches - A bit or other vector may be used to identify whether an address range entered into an intermediate buffer corresponds to most recently updated data associated with the address range. A bit or other vector may also be used to identify whether an address range entered into an intermediate buffer overlaps with an address range of data that is to be loaded. A processing device may then determine whether to obtain data that is to be loaded entirely from a cache, entirely from an intermediate buffer which temporarily buffers data destined for a cache until the cache is ready to accept the data, or from both the cache and the intermediate buffer depending on the particular vector settings. Systems, devices, methods, and computer readable media are provided. | 07-03-2014 |
20150220436 | Power Efficient Level One Data Cache Access With Pre-Validated Tags - A system and method to implement a tag structure for a cache memory that includes a multi-way, set-associative translation lookaside buffer. The tag structure may store vectors in an L | 08-06-2015 |
Niranjan Cooray, Folson, CA US
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20140189254 | Snoop Filter Having Centralized Translation Circuitry and Shadow Tag Array - A processor is described that includes a plurality of processing cores. The processor includes an interconnection network coupled to each of said processing cores. The processor includes snoop filter logic circuitry coupled to the interconnection network and associated with coherence plane logic circuitry of the processor. The snoop filter logic circuitry contains circuitry to hold information that identifies not only which of the processing cores are caching specific cache lines that are cached by the processing cores, but also, where in respective caches of the processing cores the cache lines are cached. | 07-03-2014 |
Niranjan L. Cooray, Folsom, CA US
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20110149661 | MEMORY ARRAY HAVING EXTENDED WRITE OPERATION - In some embodiments, an apparatus comprising a memory array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns and configured to receive a clock signal having a plurality of clock cycles; a plurality of word-lines associated with the plurality of rows of the SRAM cells; and a selected word-line driver configured during an extended write operation to drive a selected one of the plurality of word-lines with a write word-line signal having an extended duration. Other embodiments may be described and claimed. | 06-23-2011 |
20140101461 | PARALLELIZED COUNTER TREE WALK FOR LOW OVERHEAD MEMORY REPLAY PROTECTION - A processor includes a memory encryption engine that provides replay and confidentiality protections to a memory region. The memory encryption engine performs low-overhead parallelized tree walks along a counter tree structure. The memory encryption engine upon receiving an incoming read request for the protected memory region, performs a dependency check operation to identify dependency between the incoming read request and an in-process request and to remove the dependency when the in-process request is a read request that is not currently suspended. | 04-10-2014 |
20140181388 | Method And Apparatus To Implement Lazy Flush In A Virtually Tagged Cache Memory - A processor includes a processor core including an execution unit to execute instructions, and a cache memory. The cache memory includes a controller to update each of a plurality of stale indicators in response to a lazy flush instruction. Each stale indicator is associated with respective data, and each updated stale indicator is to indicate that the respective data is stale. The cache memory also includes a plurality of cache lines. Each cache line is to store corresponding data and a foreground tag that includes a respective virtual address associated with the corresponding data, and that includes the associated stale indicator. Other embodiments are described as claimed. | 06-26-2014 |
20150178214 | CACHE MEMORY DATA COMPRESSION AND DECOMPRESSION - A cache memory data compression and decompression technique is described. A processor device includes a memory controller unit (MCU) coupled to a main memory and a cache memory. The MCU includes a cache memory data compression and decompression module that compresses data received from the main memory. The compressed data may then be stored in the cache memory. The cache memory data compression and decompression module may also decompress data that is stored in the cache memory. For example, in response to a cache hit for data requested by a processor, the compressed data in the cache memory may be decompressed and subsequently read or operated upon by the processor. | 06-25-2015 |