| Patent application number | Description | Published |
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| 20080201681 | COMPUTER PROGRAM PRODUCTS FOR DETERMINING STOPPING POWERS OF DESIGN STRUCTURES WITH RESPECT TO A TRAVELING PARTICLE - A computer program product, comprising a computer usable medium having a computer readable program code embodied therein, said computer readable program code including an algorithm adapted to implement a method including the following steps. First, design information of the design structure is provided including a back-end-of-line layer of the integrated circuit which includes N interconnect layers, N being a positive integer. Next, each interconnect layer of the N interconnect layers is divided into multiple pixels. Next, a first path of a traveling particle in a first interconnect layer of the N interconnect layers is determined. Next, M path pixels of the multiple pixels of the first interconnect layer on the first path of the traveling particle are identified, M being a positive integer. Next, a first loss energy lost by the traveling particle due to its completely passing through a first pixel of the M path pixels is determined. | 08-21-2008 |
| 20080211100 | METHOD AND STRUCTURE FOR REDUCING CONTACT RESISTANCE BETWEEN SILICIDE CONTACT AND OVERLYING METALLIZATION - A semiconductor structure in which the contact resistance in the contact opening is reduced as well as a method of forming the same are provided. This is achieved in the present invention by replacing conventional contact metallurgy, such as tungsten, or a metal silicide, such as Ni silicide or Cu silicide, with a metal germanide-containing contact material. The term “metal germanide-containing” is used in the present application to denote a pure metal germanide (i.e., MGe alloy) or a metal germanide that includes Si (i.e., MSiGe alloy). | 09-04-2008 |
| 20080217780 | ELIMINATING METAL-RICH SILICIDES USING AN AMORPHOUS Ni ALLOY SILICIDE STRUCTURE - The present invention provides a method for producing thin nickel (Ni) monosilicide or NiSi films (having a thickness on the order of about 30 nm or less), as contacts in CMOS devices wherein an amorphous Ni alloy silicide layer is formed during annealing which eliminates (i.e., completely by-passing) the formation of metal-rich silicide layers. By eliminating the formation of the metal-rich silicide layers, the resultant NiSi film formed has improved surface roughness as compared to a NiSi film formed from a metal-rich silicide phase. The method of the present invention also forms Ni monosilicide films without experiencing any dependence of the dopant type concentration within the Si-containing substrate that exists with the prior art NiSi films. | 09-11-2008 |
| 20080217781 | ELIMINATING METAL-RICH SILICIDES USING AN AMORPHOUS Ni ALLOY SILICIDE STRUCTURE - The present invention provides a method for producing thin nickel (Ni) monosilicide or NiSi films (having a thickness on the order of about 30 nm or less), as contacts in CMOS devices wherein an amorphous Ni alloy silicide layer is formed during annealing which eliminates (i.e., completely by-passing) the formation of metal-rich silicide layers. By eliminating the formation of the metal-rich silicide layers, the resultant NiSi film formed has improved surface roughness as compared to a NiSi film formed from a metal-rich silicide phase. The method of the present invention also forms Ni monosilicide films without experiencing any dependence of the dopant type concentration within the Si-containing substrate that exists with the prior art NiSi films. | 09-11-2008 |
| 20080251284 | Electronics Structures Using a Sacrificial Multi-Layer Hardmask Scheme - An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. | 10-16-2008 |
| 20080284036 | STRUCTURE FOR OPTIMIZING FILL IN SEMICONDUCTOR FEATURES DEPOSITED BY ELECTROPLATING - A structure and process are provided that are capable of reducing the occurrence of discontinuities within the metallization, such as voiding or seams, formed during electroplating at the edges of semiconductor metallization arrays. The structure includes a metallization bar located around the periphery of the array. The process employs the structure during electroplating. | 11-20-2008 |
| 20090109722 | REPROGRAMMABLE ELECTRICAL FUSE - The present invention provides a reprogrammable electrically blowable fuse and associated design structure. The electrically blowable fuse is programmed using an electro-migration effect and is reprogrammed using a reverse electro-migration effect. The state (i.e., “opened” or “closed”) of the electrically blowable fuse is determined by a sensing system which compares a resistance of the electrically blowable fuse to a reference resistance. | 04-30-2009 |
| 20090194876 | INTERCONNECT STRUCTURE AND METHOD FOR Cu/ULTRA LOW k INTEGRATION - A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein the conductively filled via is in contact with an exposed surface of the at least one conductive feature of the first interconnect level by an anchoring area. Moreover, the conductively filled via and conductively filled line of the inventive structure are separated from the second dielectric material by a single continuous diffusion barrier layer. As such, the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line. A method of forming such an interconnect structure is also provided. | 08-06-2009 |
| 20090269929 | NON-PLASMA CAPPING LAYER FOR INTERCONNECT APPLICATIONS - The present invention provides an interconnect structure which has a high leakage resistance and substantially no metallic residues and no physical damage present at an interface between the interconnect dielectric and an overlying dielectric capping layer. The interconnect structure of the invention also has an interface between each conductive feature and the overlying dielectric capping layer that is substantially defect-free. The interconnect structure of the invention includes a non-plasma deposited dielectric capping layer which is formed utilizing a process including a thermal and chemical-only pretreatment step that removes surface oxide from atop each of the conductive features as well as metallic residues from atop the interconnect dielectric material. Following this pretreatment step, the dielectric capping layer is deposited. | 10-29-2009 |
| 20090278260 | REDUNDANCY DESIGN WITH ELECTRO-MIGRATION IMMUNITY AND METHOD OF MANUFACTURE - An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, a design structure of the IC interconnect and a method of manufacture of the IC interconnect is provided. The structure has electro-migration immunity and redundancy of design, which includes a plurality of wires laid out in parallel and each of which are coated with a liner material. Two adjacent of the wires are physically contacted to each other. | 11-12-2009 |
| 20100084766 | SURFACE REPAIR STRUCTURE AND PROCESS FOR INTERCONNECT APPLICATIONS - Semiconductor interconnect structures including a surface-repair material, e.g., a noble metal or noble metal alloy, that fills hollow-metal related defects located within a conductive material are provided. The filling of the hollow-metal related defects with the surface repair material improves the electromigration (EM) reliability of the structure as well as decreasing in-line defect related yield loss. | 04-08-2010 |
| 20110031623 | INTERCONNECT STRUCTURE AND METHOD FOR Cu/ULTRA LOW k INTEGRATION - A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein the conductively filled via is in contact with an exposed surface of the at least one conductive feature of the first interconnect level by an anchoring area. Moreover, the conductively filled via and conductively filled line of the inventive structure are separated from the second dielectric material by a single continuous diffusion barrier layer. As such, the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line. A method of forming such an interconnect structure is also provided. | 02-10-2011 |
| 20110031633 | AIR CHANNEL INTERCONNECTS FOR 3-D INTEGRATION - A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof. In addition, the 3D chip stack structure further includes one or more openings in a peripheral region of the chip stack structure that lead into and out of the air channel interconnect network, so that air can flow into and out of the air channel interconnect network through the one or more openings to remove heat from the chip stack structure. | 02-10-2011 |
| 20110080180 | VARYING CAPACITANCE VOLTAGE CONTRAST STRUCTURES TO DETERMINE DEFECT RESISTANCE - A method for determining resistances of defects in a test structure, comprising: forming a first layer of the test structure having elements under test; generating a first e-beam image of the first layer, the first e-beam image graphically identifying defects detected at the first layer, each defect at the first layer having a corresponding grey scale level; adding capacitance to the structure by forming a metal layer of the structure; generating a second e-beam image of the metal layer, the second e-beam image graphically identifying defects detected at the metal layer, each defect at the metal layer having a corresponding grey scale level; generating a pattern of grey scale levels for each defect based on the corresponding grey scale level of each defect at each layer of the test structure; and determining a resistive range of each defect based on the pattern of grey scale levels generated for each defect. | 04-07-2011 |
| 20110127438 | Dosimeter Powered by Passive RF Absorption - A system for determining an amount of radiation includes a dosimeter configured to receive the amount of radiation, the dosimeter comprising a circuit having a resonant frequency, such that the resonant frequency of the circuit changes according to the amount of radiation received by the dosimeter, the dosimeter further configured to absorb RF energy at the resonant frequency of the circuit; a radio frequency (RF) transmitter configured to transmit the RF energy at the resonant frequency to the dosimeter; and a receiver configured to determine the resonant frequency of the dosimeter based on the absorbed RF energy, wherein the amount of radiation is determined based on the resonant frequency. | 06-02-2011 |
| 20110133163 | NANOWIRE FET HAVING INDUCED RADIAL STRAIN - An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire. | 06-09-2011 |
| 20110133166 | NANOWIRE FET HAVING INDUCED RADIAL STRAIN - A device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads and a gate including a gate conductor surrounding the nanowire and a fully silicided material surrounding the gate conductor to radially strain the nanowire. | 06-09-2011 |
