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Collados Asensio
Manel Collados Asensio, Ga Eindhoven NL
| Patent application number | Description | Published |
|---|---|---|
| 20120019296 | Circuit With a Time to Digital Converter and Phase Measuring Method - Calibration data for calibrating time to digital conversion is obtained by switching a feed circuit ( | 01-26-2012 |
Manuel Collados Asensio, Ag Eindhoven NL
| Patent application number | Description | Published |
|---|---|---|
| 20100052806 | MODULATION FOR AMPLITUDE-MODULATING A SIGNAL - Modulators for amplitude-modulating signals defined by phase information and envelope codes are provided with first transistors for receiving the phase information and second transistors for receiving the envelope codes. The first main electrode of one transistor is coupled to the second main electrode of the other transistor and the other second main electrode constitutes an output of the modulator. This modulator can be used in any kind of transistor environment and is simple and low cost. The doped areas of the coupled first and second main electrodes comprise an overlap to reduce cross-talk and to reduce silicon area. Polar transmitters are provided with this modulator and with a circuit for generating a phase/frequency code and the envelope code and with an oscillator for receiving the phase/frequency code and for generating the phase information. A phase shift between the phase information and the envelope code reduce aliases. | 03-04-2010 |
Manuel Collados Asensio, Larkfield GB
| Patent application number | Description | Published |
|---|---|---|
| 20110261914 | Digital Modulator - The present application relates to a digital modulator comprising an output stage comprising a number of unit cell arrays, and a sampling stage. The present application relates also to a communication device comprising said digital modulator, a method for digitally modulating and a computer program product. More particularly, the digital modulator comprises an output stage comprising a number of unit cell arrays, wherein the output stage comprises at least one carrier frequency signal input terminal configured to receive a carrier frequency signal. The digital modulator comprises a sampling stage connectable to the output stage, wherein the sampling stage is configured to oversample at least one data input signal. The digital modulator comprises at least one sampling clock generating device configured to generate at least one sampling clock signal depending on the number of arranged unit cell arrays and the carrier frequency signal. | 10-27-2011 |