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Colburn, NY
Jeffrey B. Colburn, Harpursville, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090085368 | TACTICAL TRUCK SYSTEM DASHBOARD - A dashboard for a tactical vehicle having a driver position and a passenger position. The dashboard includes a plurality of panels removably attached together to form a dashboard having a plurality of displays and warning lights viewable from the driver position to provide information for the driver of a vehicle. One of the panels is located in front of the vehicle driver position and has a driver instrument cluster. | 04-02-2009 |
Mathew E. Colburn, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090008791 | Circuit Structure with Low Dielectric Constant Regions - A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects. | 01-08-2009 |
Matthew Colburn, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080199816 | Method of Automatic Fluid Dispensing for Imprint Lithography Processes - Disclosed herein is an automatic fluid dispensing method and system for dispensing fluid on the surface of a plate-like material, or substrate, including a semiconductor wafer for imprint lithography processes. The dispensing method uses fluid dispenser and a substrate stage that may generate relative lateral motions between a fluid dispenser tip a substrate. Also described herein are methods and devices for creating a planar surface on a substrate using a substantially unpatterned planar template. | 08-21-2008 |
| 20100173033 | Device for Holding a Template for Use in Imprint Lithography - An imprint lithography template may be used to form an imprinted layer in a light curable liquid disposed on a substrate. During use, the template may be disposed within a template holder. The template holder may include a body with an opening configured to receive the template, a support plate, and an actuator system coupled to the body. The actuator system may be configured to alter a physical dimension of the template during use. | 07-08-2010 |
Matthew Colburn, Schenectady, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090239334 | ELECTRODE FORMED IN APERTURE DEFINED BY A COPOLYMER MASK - A method of manufacturing a memory device is provided that in one embodiment includes providing an interlevel dielectric layer including a first via containing a memory material; forming at least one insulating layer on an upper surface of the memory material and the interlevel dielectric layer; forming an cavity through a portion of a thickness of the at least one insulating layer; forming a copolymer mask in at least the cavity, the copolymer mask including at least one opening that provides an exposed surface of a remaining portion of the at least one insulating layer that overlies the memory material; etching the exposed surface of the remaining portion of the at least one insulating layer to provide a second via to the memory material; and forming a conductive material within the second via in electrical contact with the memory material. | 09-24-2009 |
Matthew E. Colburn, Albany, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110049680 | DUAL EXPOSURE TRACK ONLY PITCH SPLIT PROCESS - An integrated circuit is formed with structures spaced more closely together than a transverse dimension of such structures, such as for making contacts to electronic elements formed at minimum lithographically resolvable dimensions by dark field split pitch techniques. Acceptable overlay accuracy and process efficiency and throughput for the split pitch process that requires etching of a hard mark for each of a plurality of sequentially applied and patterned resist layers is supported by performing the etching of the hard mask entirely within a lithography track through using an acid sensitive hard mark material and an acidic overcoat which contacts areas of the hard mask through patterned apertures in the resist. The contacted areas of the hard mask are activated for development by baking of the acidic overcoat. | 03-03-2011 |
Matthew E. Colburn, Schenecctady, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100178615 | METHOD FOR REDUCING TIP-TO-TIP SPACING BETWEEN LINES - This invention provides a method for reducing tip-to-tip spacing between lines using a combination of photolithographic and copolymer self-assembling lithographic techniques. A mask layer is first formed over a substrate with a line structure. A trench opening of a width d is created in the mask layer. A layer of a self-assembling block copolymer is then applied over the mask layer. The block copolymer layer is annealed to form a single unit polymer block of a width or a diameter w which is smaller than d inside the trench opening. The single unit polymer block is selectively removed to form a single opening of a width or a diameter w inside the trench opening. An etch transfer process is performed using the single opening as a mask to form an opening in the line structure in the substrate. | 07-15-2010 |
Matthew E. Colburn, Armonk, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110129652 | Chemical Trim of Photoresist Lines by Means of A Tuned Overcoat - A new lithographic process comprises reducing the linewidth of an image while maintaining the lithographic process window, and using this process to fabricate pitch split structures comprising nm order (e.g., about 22 nm) node semiconductor devices. The process comprises applying a lithographic resist layer on a surface of a substrate and patterning and developing the lithographic resist layer to form a nm order node image having an initial line width. Overcoating the nm order node image with an acidic polymer produces an acidic polymer coated image. Heating the acidic polymer coated image gives a heat treated coating on the image, the heating being conducted at a temperature and for a time sufficient to reduce the initial linewidth to a subsequent narrowed linewidth. Developing the heated treated coating removes it from the image resulting in a free-standing trimmed lithographic feature on the substrate. Optionally repeating the foregoing steps further reduces the linewidth of the narrowed line. The invention also comprises a product produced by this process. | 06-02-2011 |
Matthew E. Colburn, Schenectedy, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20120058640 | METHOD FOR FORMING AN INTERCONNECT STRUCTURE - A method for forming an interconnect structure includes forming a mandrel above a base layer, forming spacers on the mandrel, forming recesses in the base layer using the spacers as an etch template, and forming a conductive material in the recesses. | 03-08-2012 |
Matthew Earl Colburn, Schenectady, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090093114 | METHOD OF FORMING A DUAL-DAMASCENE STRUCTURE USING AN UNDERLAYER - A method of forming a dual-damascene wire. The method includes forming a via opening in a dielectric layer, filling the via opening with a polymeric formation including at least about 6% by weight of solids of thermal acid generator; heating the polymeric underlayer to a temperature greater than room temperature but less than about 180° C.; lithographically forming a trench in the dielectric layer and filling the via opening and the trench with an electrical conductor, a top surface of the electrical conductor substantially co-planer with the top surface of the second dielectric capping layer. | 04-09-2009 |
Matthew Earl Colburn, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080251284 | Electronics Structures Using a Sacrificial Multi-Layer Hardmask Scheme - An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. | 10-16-2008 |
| 20090200683 | INTERCONNECT STRUCTURES WITH PARTIALLY SELF ALIGNED VIAS AND METHODS TO PRODUCE SAME - An interconnect structure having partially self aligned vias with an interlayer dielectric layer on a substrate, containing at least two conducting metal lines that traverse parallel to the substrate and at least two conducting metal vias that are orthogonal to the substrate. A method of producing the self aligned vias by depositing an interlayer dielectric layer onto a substrate, depositing at least one hardmask onto the interlayer dielectric layer, lithographically forming a via pattern with elongated via features and lithographically forming a line pattern in either order, then either transferring the line patterns first into the interlayer dielectric layer forming line features or transferring the via pattern first into the interlayer dielectric layer as long as the patterns overlap to forming self aligned via features, depositing conducting metals and filling regions corresponding to the line and via features, and planarizing and removing excess metal from the line and via features. | 08-13-2009 |