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Codina, ES
Enric Gibert Codina, Sant Cugat Del Valles ES
| Patent application number | Description | Published |
|---|---|---|
| 20100262812 | REGISTER CHECKPOINTING MECHANISM FOR MULTITHREADING - Methods and apparatus are disclosed for using a register checkpointing mechanism to resolve multithreading mis-speculations. Valid architectural state is recovered and execution is rolled back. Some embodiments include memory to store checkpoint data. Multiple thread units concurrently execute threads. They execute a checkpoint mask instruction to initialize memory to store active checkpoint data including register contents and a checkpoint mask indicating the validity of stored register contents. As register contents change, threads execute checkpoint write instructions to store register contents and update the checkpoint mask. Threads also execute a recovery function instruction to store a pointer to a checkpoint recovery function, and in response to mis-speculation among the threads, branch to the checkpoint recovery function. Threads then execute one or more checkpoint read instructions to copy data from a valid checkpoint storage area into the registers necessary to recover a valid architectural state, from which execution may resume. | 10-14-2010 |
| 20100269102 | SYSTEMS, METHODS, AND APPARATUSES TO DECOMPOSE A SEQUENTIAL PROGRAM INTO MULTIPLE THREADS, EXECUTE SAID THREADS, AND RECONSTRUCT THE SEQUENTIAL EXECUTION - Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retire instructions of the speculatively executed threads in the MLC. | 10-21-2010 |
Josep M. Codina, Barcelona ES
| Patent application number | Description | Published |
|---|---|---|
| 20100269102 | SYSTEMS, METHODS, AND APPARATUSES TO DECOMPOSE A SEQUENTIAL PROGRAM INTO MULTIPLE THREADS, EXECUTE SAID THREADS, AND RECONSTRUCT THE SEQUENTIAL EXECUTION - Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retire instructions of the speculatively executed threads in the MLC. | 10-21-2010 |
Josep M. Codina, Hospitalet De Llobregat ES
| Patent application number | Description | Published |
|---|---|---|
| 20090150335 | ACHIEVING COHERENCE BETWEEN DYNAMICALLY OPTIMIZED CODE AND ORIGINAL CODE - An apparatus comprising a first search logic to search for a first entry for a first page containing a first code region in a first data structure to determine whether a first indicator in the first entry is set to a first value; an adder logic to add the first entry to the first data structure, in response to failing to find the first entry in the first data structure; a second search logic to search for a second entry for the first code region in a second data structure, in response to determining that the first indicator is set to the first value, wherein one or more optimized code regions corresponding to the first page from a code cache are to be removed in response to determining that the first page may have been modified, and wherein the first indicator is to be set to a second value. | 06-11-2009 |
| 20100005277 | Communicating Between Multiple Threads In A Processor - In one embodiment, the present invention includes a method for accessing registers associated with a first thread while executing a second thread. In one such embodiment a method may include preventing an instruction of a first thread that is to access a source operand from a register file of a second thread from executing if a synchronization indicator associated with the source operand indicates incompletion of a producer operation of the second thread, and executing the instruction if the synchronization indicator indicates completion of the producer operation of the second thread. Other embodiments are described and claimed. | 01-07-2010 |
| 20100262812 | REGISTER CHECKPOINTING MECHANISM FOR MULTITHREADING - Methods and apparatus are disclosed for using a register checkpointing mechanism to resolve multithreading mis-speculations. Valid architectural state is recovered and execution is rolled back. Some embodiments include memory to store checkpoint data. Multiple thread units concurrently execute threads. They execute a checkpoint mask instruction to initialize memory to store active checkpoint data including register contents and a checkpoint mask indicating the validity of stored register contents. As register contents change, threads execute checkpoint write instructions to store register contents and update the checkpoint mask. Threads also execute a recovery function instruction to store a pointer to a checkpoint recovery function, and in response to mis-speculation among the threads, branch to the checkpoint recovery function. Threads then execute one or more checkpoint read instructions to copy data from a valid checkpoint storage area into the registers necessary to recover a valid architectural state, from which execution may resume. | 10-14-2010 |
Josep M. Codina, Llobregat ES
| Patent application number | Description | Published |
|---|---|---|
| 20100115247 | REPLACEMENT POLICY FOR HOT CODE DETECTION - Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution frequency information corresponding to the hot code. Other embodiments are also described and claimed. | 05-06-2010 |
Victor Codina, Girona ES
| Patent application number | Description | Published |
|---|---|---|
| 20090100094 | Recommendation system and method for multimedia content - A recommendation method for multimedia content and a computer program for performing the method includes in one aspect the steps of obtaining at least two lists of recommended titles, each list being obtained according to a different approach, base on a user database and a content database, combining the at least two lists of recommended titles so obtained based on confidence levels in order to obtain a final list of recommended titles, and recommending the final list of recommended titles to a user. | 04-16-2009 |